Part Number: ADC121S101CIMFX/NOPB

Manufacturer: Texas Instruments

Description: IC ADC 12BIT SAR SOT23-6

Shipped from: Shenzhen/HK Warehouse

Stock Available: Check with us

Technical Specifications of ADC121S101CIMFX/NOPB

Datasheet  ADC121S101CIMFX/NOPB datasheet
Category Integrated Circuits (ICs)
Family Data Acquisition – Analog to Digital Converters (ADC)
Manufacturer Texas Instruments
Packaging Tape & Reel (TR)
Part Status Active
Number of Bits 12
Sampling Rate (Per Second) 1M
Number of Inputs 1
Input Type Single Ended
Data Interface SPI, DSP
Configuration S/H-ADC
Ratio – S/H:ADC 1:1
Number of A/D Converters 1
Architecture SAR
Reference Type Supply
Voltage – Supply, Analog 2.7 V ~ 5.25 V
Voltage – Supply, Digital 2.7 V ~ 5.25 V
Operating Temperature -40°C ~ 125°C
Package / Case SOT-23-6
Supplier Device Package SOT-23-6

ADC121S101CIMFX/NOPB Description

The ADC121S101 is a high-speed serial interface, low-power, single-channel CMOS 12-bit A/D converter. The ADC121S101 is completely specified over a sample rate range of 500 ksps to 1 Msps, which contrasts the standard practice of just describing performance at a single sample rate. The converter uses a track-and-hold circuit built into its register design for successive approximation.

Straight binary serial data is output, compatible with various serial interface standards, including those used by many common DSPs. All that’s needed to power the ADC121S101 is a single supply between 2.7 V and 5.25 V. When operating from a 3 V or 5 V source, and typical power usage is 2 mW and 10 mW, respectively. Using a 5-V supply, the power-down function reduces power consumption to as little as 2.6 W. The ADC121S101 comes in SOT-23 and WSON 6-pin packaging. This product is guaranteed to function between temperatures of -40 degrees Celsius and 125 degrees Celsius.

ADC121S101CIMFX/NOPB Features

  • Predicted Over a Wide Bandwidth of Sample Rates
  • Including 6-Pin WSON and SOT-23 Cases
  • Dynamic Power Control
  • All-in-One 2.7 V–5.25 V Volt Power Supply
  • Modular Interface Supporting SPITM, QSPITM, MICROWIRE, and DSP
  • Grade 1 AEC-Q100 DNL with qualifications: +0.5 / 0.3 LSB (Typical)
  • LSB: 0.40 INL (Typical)


  • Portable Systems
  • Remote Data Acquisition
  • Instrumentation and Control Systems
  • Automotive

Device Functional Modes

The ADC can be used in either its usual or shutdown mode. When CS is brought low, the ADC enters the usual way (and the conversion process begins). If CS is not held low and is pushed high before the tenth falling edge of SCLK, the device will enter shutdown mode. A device that has entered shutdown mode will remain in that state until the CS is again brought down. The sampling rate need not be greater than zero for a system to trade off throughput for power consumption by adjusting the ratio of time spent in the regular and shutdown modes.

● Normal Mode

Keeping the ADC in normal mode at all times eliminates power-up delays, allowing for maximum throughput. Continuous regular operation of the device requires that CS be held low until after the 10th falling edge of SCLK following the beginning of a conversion (remember that a transformation is initiated by bringing CS low). If CS is asserted after the 10th falling edge and before the 16th falling edge, the device will continue to function normally; otherwise, the current conversion will be aborted, and SDATA will revert to TRI-STATE (truncating the output word).

Sixteen SCLK cycles are needed to read an entire conversion word from the hardware. To wait for the following conversion, CS can be idled high or low for 16 SCLK cycles. After a period of low CS idle, the next conversion cycle will commence once CS is again brought to a low state. SDATA transitions back to TRI-STATE after being in TRI-STATE for 16 SCLK cycles. After tQUIET has passed, you can initiate a second conversion by lowering CS once more.

● Shutdown Mode

Applications that can afford to sacrifice throughput for power consumption can benefit from shutdown mode. All analog circuitry is disabled when the ADC is in a power-down way.

Power Supply

Recommendations A capacitor network near the ADC bypasses the power supply pin. ADCs use the supply voltage as a reference, so any noise on the supply will result in less than optimal noise performance from the device. Suppose you want to prevent noise from entering the ADC. In that case, you should either use a linear regulator specifically designed for this device or isolate the supply port from other circuitry. As a bonus, the ADC’s low power consumption means that a precise reference for optimal efficiency can power it.

Power Management

It takes some time for the ADC to power up, whether you are applying VA for the first time or coming back to normal mode after being in shutdown mode. This equates to one dummy conversion for any SCLK frequency that falls within the parameters of the standards presented in this document. Following this initial conversion of false data, the ADC will correctly perform conversions. It is important to remember that the tQUIET time must still be included somewhere between the first fake conversion and the second legitimate conversion. The ADC may power on in either the normal mode or the shutdown mode, depending on which mode it was in when the VA supply was initially applied.

Consequently, it is necessary to carry out one fake conversion after start-up, as explained in the preceding paragraph. After that, the component can be set to operate in either the normal mode or the shutdown mode, as detailed in Normal Mode and Shutdown Mode, respectively. At the highest possible fSCLK frequency, the maximum throughput of the ADC is equal to fSCLK divided by 20 when it is operating continuously in normal mode. By running fSCLK at its maximum specified rate, performing fewer conversions per unit of time, and raising the ADC CS line after the 10th and before the 15th fall of SCLK of each conversion, it is possible to trade throughput for power consumption. This can be done by running fSCLK at its maximum specified rate.


VA is needed to charge any output load capacitance. Voltage variations in the supply result from current pulses required to charge the output capacitance. These fluctuations could lower the ADC’s SNR and SINAD. When the digital output swings from logic high to logic low, the output capacitance discharges, dumping current into the resistive die substrate.

When load discharge currents are high enough, substrate ground bounce noise reduces noise performance. More current flows through the device substrate, and more noise is linked into the analog channel as output capacitance increases. Minimize the output load capacitance to reduce power supply noise. A 100-Ohm series resistor near the ADC output pin is recommended. This restricts charging and discharge current.

If you require any information or would like to place an order for the AT25SF321-SHD-T, please contact ICRFQ, your one-stop shop for electronic sourcing components in China. We are committed to putting in the effort necessary to ensure that you are provided with the highest quality goods at the most competitive pricing.

4.8/5 - (397 votes)
Kevin Chen