AT24C16C-PUM

AT24C16C-PUM

Part Number: AT24C16C-PUM

Manufacturer: Microchip Technology

Description: EEPROM SERIAL EEPROM 16K (2K X 8) 2-WIRE 1.7V

Shipped from: Shenzhen/HK Warehouse

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AT24C16C-PUM Description

Description The AT24C16C includes 2,048 words of 8 bits each, for a total of 16,384 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM). It is great for many business and manufacturing uses because it uses little power and low operating voltage. The component can be purchased in different small form factor packages, including 8-pad UDFN, 8-pad XDFN, 5-lead SOT23, 8-pad PDIP, 8-pad UDFN, and 8-pad TSSOP. All models can function between 1.7V and 5.5V.

Product Features

  • Compatibility with 400 kHz and 1 MHz clocks at 2K x 8 (16 Kbit)
  • Automatic Erasing and Writing Cycles (5 ms max.)
  • One ma, read current of 0.4 ma (Typ) (Max)
  • Write current (Typ) two ma, three ma. (Max)
  • Hardware Pin to protect writing
  • More than a million times, when you write and erase
  • > 100 years of data preservation
  • The temperature range for Grade 1 is -40°C to 125°C.
  • The temperature range for grade 2 is -40°C to 105°C.
  • -40°C to 85°C is the temperature range for grade 3.
  • Automotive Applications Factory Programming Competent Available

Device Operation and Communication

The Inter-Integrated Circuit (I2C) bus standard is compatible with the AT24C16C, which communicates with the bus master via a 2-wire digital serial interface. The master and the secondary devices can send and receive data using a serial bus, but only the master can start read-and-write operations. The only two signal lines that comprise the serial interface are the serial clock (SCL) and serial data (SDA) (SDA). The SCL pin is used to receive the master clock, and the SDA pin, which can also be used to communicate with the master, is used to receive and transmit command and data information.

Data is always latched by the AT24C16C on the SCL’s rising edge and released on its descent. Spike suppression filters and Schmitt triggers are built into SCL and SDA, respectively, to reduce the impact of input spikes and bus noise. The Most Significant Bit (MSb) of each command and piece of data is sent first. The slave device will respond to the ninth clock cycle produced by the master device by sending either an Acknowledge (ACK) or a No-Acknowledge (NACK) response bit. The master device will then have delivered eight data bits (one byte) to the slave device. Each data byte requires nine cycles to transmit since there are nine clock cycles.

There are no unused clock cycles during any read or write operation; therefore, there must be no interruptions in the data stream between each byte transfer and each ACK or NACK clock cycle. Data on the SDA pin should be stable when SCL is high and vice versa during data transfers. Data on the SDA pin will change if SCL is high and SDA is low, resulting in a Start or Stop condition. On the serial bus, all communication between the slave and master devices begins and ends in response to the start and stop of infections. The master controls the maximum number of bytes transferred between a Start and Stop condition. To stop serial bus activity, the SCL and SDA pins must be in high logic states.

Clock and Data Transition Requirements

Because it is an open-drain terminal, the SDA pin needs an external pull-up resistor to be set to its high state. An external pull-up resistor can force SCL, an input pin, to a high state. SCL must be low for the SDA pin to be updated. Variations in the data during SCL peak times signify a Start or Stop condition, respectively.

Start and Stop Conditions

● Start Condition

A start condition is when the SDA pin changes from high to low while the SCL pin stays steady at logic 1, at which point the device exits standby mode. Because the master will start a data transfer sequence with a Start condition, each command must start with one. Before acting, this device will wait for a Start condition to be found on the SDA and SCL pins.

● Stop Condition

A stop condition occurs when the SDA pin changes from low to high while the SCL pin stays in the logic state. After receiving a Stop condition from the master, the AT24C16C will leave Active mode and return to standby. Instead of repeatedly issuing a Stop condition, the master can do this if it needs to complete another task before concluding the current data transfer.

The Difference Between Accepting and Refusing Responsibility The receiver sends a confirmation signal known as an acknowledgement to the sender to confirm that it has received each byte of data (ACK). The receiver responds with a logic 0 for the ninth clock cycle to complete an ACK after the sender releases the SDA line on the falling edge of the eighth clock cycle.

For instance, if the master is receiving data from the AT24C16C and is prepared to end the operation, it can send a logic one response in place of an ACK response to the AT24C16C’s ninth clock cycle transmission. The AT24C16C will release the SDA line and permit the master to generate a Stop condition after receiving a logic one from the master on the ninth clock cycle, which is required to achieve this. We call this a No-Acknowledge (NACK).

The device sending the data must release the SDA line at the falling edge of the eighth clock cycle so that the device receiving it can set it to logic zero and ACK the preceding 8-bit word. After the ninth clock cycle, the receiver must let go of the SDA line so the transmitter can keep sending data.

Conclusion

A 16Kb Serial EEPROM using an I2C (2-wire) serial interface is the Microchip AT24C16C. The system is set up as a single 2K x 8 block and designed with reliability and dependability in mind for the consumer, business, and automotive applications. Several options for packaging the EEPROM that saves space are available.

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