AT25SF321-SHD-T

AT25SF321-SHD-T

Part Number: AT25SF321-SHD-T

Manufacturer: Adesto Technologies

Description: NOR Flash 32 Mbit, 3.0V (2.5V to 3.6V)

Shipped from: Shenzhen/HK Warehouse

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AT25SF321-SHD-T Description

The Adesto® AT25SF321 is a serial interface Flash memory device designed for a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SF321 is also ideal for data storage, eliminating the need for additional data storage devices. The erase block sizes of the AT25SF321 have been optimized to meet the needs of today’s code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently.

Because certain code modules and data storage segments must reside by themselves in their own erase regions. This wasted and unused memory space occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while maintaining the same overall device density. The device also contains three pages of Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register pages can be individually locked.

Device Operation

The AT25SF321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25SF321 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF321 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK.

Dual Output Read

The AT25SF321 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

Quad Output Read

The AT25SF321 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO pin.

Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25SF321 will be ignored by the device and no operation will be started.

The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the upper address limit of the AT25SF321 memory array is 3FFFFFh, address bits A23-A22 are always ignored by the device.

Security Register Commands

The device contains three extra pages called Security Registers that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are independent of the main Flash memory. Each page of the Security Register can be erased and programmed independently. Each page can also be independently locked to prevent further changes.

Erase Security Registers (44h) Before an erase Security Register Page command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. To perform an Erase Security Register Page command, the CS pin must first be asserted and the opcode 44h must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying the Security Register Page to be erased must be clocked in. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and should take place in a time of tBE. Since the Erase Security Register Page command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore address bits A7-A0 will be ignored by the device.

Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise, the device will abort the operation and no erase operation will be performed. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBE time to determine if the device has finished erasing. At some point before the erase cycle completes, the RDY/BSY bit in the Status Register will be reset back to the logical “0” state.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. The Security Registers Lock Bits (LB3-LB1) in the Status Register can be used to OTP protect the security registers. Once a Lock Bit is set to 1, the corresponding Security Register will be permanently locked. The Erase Security Register Page instruction will be ignored for Security Registers with Lock Bit set.

Conclusion

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