ATMEGA328P-AU IC

Technical Specifications of ATMEGA328P-AU

Datasheet	ATMEGA328P-AU datasheet
Category	Integrated Circuits (ICs)
Family	Embedded – Microcontrollers
Manufacturer	Atmel
Series	AVR? ATmega
Packaging	Tray
Part Status	Active
Core Processor	AVR
Core Size	8-Bit
Speed	20MHz
Connectivity	I2C, SPI, UART/USART
Peripherals	Brown-out Detect/Reset, POR, PWM, WDT
Number of I/O	23
Program Memory Size	32KB (16K x 16)
Program Memory Type	FLASH
EEPROM Size	1K x 8
RAM Size	2K x 8
Voltage – Supply (Vcc/Vdd)	1.8 V ~ 5.5 V
Data Converters	A/D 8x10b
Oscillator Type	Internal
Operating Temperature	-40°C ~ 85°C (TA)
Package / Case	32-TQFP
Supplier Device Package	32-TQFP (7×7)

ATMEGA328P-AU Introduction

The AVR® improved RISC architecture is utilized in developing the 8-bit CMOS microcontrollers known as the ATmega48A/PA/88A/PA/328/P. These microcontrollers consume a minimal amount of power while simultaneously running efficiently. The devices execute instructions in a single clock cycle, which results in a CPU throughput that is near to one million instructions per second (MIPS) for each megahertz of frequency. This is done to maximize power consumption versus processing speed.

ATMEGA328P-AU Features

• Family of AVR® 8-Bit Microcontrollers with High Performance and Low Power.
• Contemporary RISC architecture.

131 Effective Instructions – Most Executed in a Single Clock Cycle.

General Purpose Working Registers, 32 x 8.

Complete Static Operation

Throughput of up to 20 MIPS at 20MHz.

2-cycle On-Chip Multiplier.

Non-volatile memory segments with high endurance.

Family of AVR® 8-Bit Microcontrollers with High Performance and Low Power.

Contemporary RISC architecture.

131 Effective Instructions – Most Executed in a Single Clock Cycle.

General Purpose Working Registers, 32 x 8.

Complete Static Operation

Throughput of up to 20 MIPS at 20MHz.

2-cycle On-Chip Multiplier.

Non-volatile memory segments with high endurance.

Independent Lock Bits in the Optional Boot Code Section.

Programming Lock for Software Security. True Read-While-Write Operation.

Support for QTouch® library.

QTouch and QMatrixTM acquisition; capacitive touch buttons, sliders, and wheels.

64 or more sense channels.

Overview

The AVR improved RISC architecture is the foundation for the low-power CMOS 8-bit microcontroller known as the ATMEGA328P-AU. At speeds close to 1 MIPS per MHz, the ATMEGA328P-AU achieves this by completing the processing of powerful instructions in a single clock cycle. This enables the system designer to optimize power consumption while maintaining a high processing performance level.

● AVR CPU Core

The execution of programs correctly is the primary responsibility of the central processing unit (CPU) core. As a result, the central processing unit (CPU) needs to have the ability to access memories, carry out calculations, operate peripherals, and respond to interrupts.

● ALU – Arithmetic Logic Unit T

All 32 of the working registers that are employed for general purposes are constantly kept in direct communication with the high-performance AVR ALU. A single clock cycle is necessary to complete an arithmetic operation between general-purpose registers or between a register and an instant. The arithmetic, logical, and bit-functions operations that the ALU performs can be divided into three main categories. Some architecture implementations feature a powerful multiplier that supports signed and unsigned multiplication and fractional format.

● Status Register

You can find the result of the most recent arithmetic instruction in the Status Register. This data can be utilized to execute conditional operations in the application. The Status Register is updated following each ALU operation, as detailed in the Instruction Set Reference. This will make the code faster and smaller by eliminating the requirement for specific compare instructions in many situations. When entering an interrupt routine, the Status Register is not saved and restored automatically. Software is required to manage this.

● Stack Pointer

Temporary data, local variables, and return addresses from interrupts and subroutine calls are all common uses for the Stack. The Stack is constructed to increase size as it moves down the memory address range. The Stack Pointer Register always indicates a stack’s top. The Subroutine Stack and the Interrupt Stack are stored in the Stack section of the data SRAM, which is indicated by the Stack Pointer. The value of the Stack Pointer is decreased when the PUSH command is sent.

● AVR Memories

Data Memory and Program Memory are the two primary types of memory used by the AVR design. The EEPROM Memory of the ATmega48A/PA/88A/PA/168A/PA/328/P allows for additional storage space. These three types of memory all follow the same linear, consistent pattern.

● Clock Output Buffer

The CLKO pin can provide the system clock from the device. The output can be activated by setting the CKOUT Fuse. In this configuration, the chip clock can be used to power other system components. In addition to the normal operation of the I/O pin being overridden during reset, the clock will also be output if the fuse is adjusted to allow for this. When using CLKO as an output, you can choose to have the clock come from any available source, including the onboard RC Oscillator. If you employ the System Clock Prescaler, the resultant divided system clock is what you get.

● Idle Mode

The SLEEP command puts the MCU into Idle mode by setting the SM2…0 bits to 000. This disables the CPU but keeps the rest of the peripherals running, including SPI, USART, ADC, Analog Comparator, Timer/Counters,  2-wire Serial Interface, Watchdog, and the interrupt system. In this sleep mode, clkCPU and clkFLASH are effectively disabled, while all other clocks operate normally. Internal interrupts, such as Timer Overflow and USART Transmit Complete, might wake the MCU in idle mode. By setting the ACD bit in the ACSR (Analog Comparator Control and Status Register), the Analog Comparator can be disabled from waking up on interrupt. As a result, power consumption while doing nothing will decrease. When switched to this mode, a conversion will begin immediately if the ADC is active.

● Minimizing Power Consumption

Attempting to reduce power usage in an AVR-controlled system can be done in several ways. Sleep modes should be utilized frequently, with the utmost care taken to ensure that as few of the device’s features are active during sleep. Inactive features should be turned off. This quest for minimum power usage may require special attention to the following modules.

SS Pin Functionality

● Slave Mode

The SPI Slave mode always has the SS pin connected to an input. If the user has set up MISO as an output, then holding SS low will activate the SPI. The remaining pins are inputs. When SS is high, the SPI is inactive, and all pins behave as inputs, but no data is received. Keep in mind that setting the SS pin high will reset the SPI logic. When synchronizing packets or bytes, the SS pin ensures that the slave bit counter remains locked with the master clock source. The SPI slave will discard any data in the Shift Register that was partially received when the SS pin is driven high.

● USART Initialization

USART must be initialized before any communication takes place. During initialization, select the appropriate baud rate, frame format, and transmitter or receiver based on how it will be used. To use the USART in an interrupt-driven fashion, it is necessary to reset the Global Interrupt Flag and turn off interrupts during initialization. Make sure there are no active transmissions before switching registers.

The TXCn Flag and the RXC Flag ensure that the receiver’s buffer is empty after each transfer. The TXCn Flag must be reset before UDRn can be written if it is to be used for transmission. The following code snippets for initializing the USART chip are simplified versions of the same thing written in C.

Conclusion

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