ATMEGA32U4-AU

ATMEGA32U4-AU

Part Number: ATMEGA32U4-AU

Manufacturer: Microchip Technology

Description: IC MCU 8BIT 32KB FLASH 44TQFP

Shipped from: Shenzhen/HK Warehouse

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ATMEGA32U4-AU Overview

Minimal power is consumed by the 8-bit CMOS operation of the AVR-based microcontrollers ATmega16U4/ATmega32U4, which are based on the AVR-improved RISC architecture. Using powerful instructions executed in a single clock cycle, the device delivers throughputs close to 1 MIPS per MHz, providing system designers additional leeway in balancing power consumption and processing performance.

ATMEGA32U4-AU Features

  • 8-bit AVR® microcontroller with high performance and low power.
  • Sophisticated RISC architecture.
  • Memory for non-volatile programs and data.
  • JTAG (IEEE® standard 1149.1) Interface.
  • Device Module for USB 2.0 Full-speed/Low-Speed with Interrupt on Transfer Completion.

Feature Description

I/O Memory

The I/O area houses all of the input/output devices and peripherals. Moving data between the 32 general-purpose working registers and the I/O space is possible using the LD/LDS/LDD and ST/STS/STD instructions. These instructions allow access to all I/O locations. Using the SBI and CBI instructions, you can directly access the bits of the I/O Registers that are located within the address range of 0x00 to 0x1F. The SBIS and SBIC instructions can be utilized to check the value of individual bits inside these registers. For further information, please refer to the part that contains the instructions. When working with the I/O-specific commands IN and OUT, the range of I/O addresses from 0x00 to 0x3F must be utilized.

It is necessary to append 0x20 to the addresses to access the I/O Registers through the LD and ST instructions. The component in question is a sophisticated microcontroller with more peripheral units that can be accommodated inside the 64 places in the opcode set aside for the IN and OUT instructions. Only the ST/STS/STD and LD/LDS/LDD instructions may be used in the SRAM location known as the Extended I/O area, which extends from 0x60 to 0xFF. When the reserved bits are accessed, they should be set to zero to ensure compatibility with future devices.

There should never be any writing done to reserved I/O memory addresses. By assigning a logical value to certain Status Flags, it is possible to clear those flags. It is essential to remember that, in contrast to most other AVRs, the CBI and SBI instructions will only operate on the given bit. As a result, they can be used on registers that include Status Flags. Only records ranging from 0x00 to 0x1F can be used with the CBI and SBI instructions.

General Purpose I/O Registers

The underlying circuitry has three GPIO Registers, each of which can be used. The information saved in these registers is applicable everywhere; nevertheless, their primary purpose is to serve as storage locations for global variables and Status Flags. Direct bit access to General Purpose I/O Registers located at addresses between 0x00 and 0x1F can be obtained using the SBI, CBI, SBIS, and SBIC instructions.

Clock Switch

The device comes with an in-built Clock Switch controller, which allows the user to switch between two separate clock sources while the application is running. Because of this, management of an application’s energy consumption and the time it spends running may be done on a more granular level.

Example of use

You may need to make the necessary modification when the device enters USB Suspend mode. The system gets rid of the external Clock in favor of a calibrated RC oscillator to save energy and cut down on the time it takes to wake up. In this configuration, the External Clock feature has been turned off. To determine whether or not the application has come across an event, the firmware can be roused from a power-down state by using the watchdog timer. This allows the firmware to check for the occurrence of an event.

When an application event occurs or the USB controller indicates a non-idle status on the USB line, In order to get the USB operations going again, the firmware will change the Clock Multiplexer from using the calibrated RC oscillator to the external clock. This is done to ensure that the USB activities are properly continued (Resume, for example). This function is limited to selecting between the Calibrated 8MHz RC Oscillator, the External Clock, and the Low Power Crystal Oscillator. It is strongly recommended that you should not combine this capability with the Low-Frequency Crystal Oscillator.

Clock Output Buffer

The gadget has a CLKO pin where the system clock can be output. The output can be activated by setting the CKOUT Fuse. This mode is appropriate when the chip clock is used to power other system circuits. Fuse programming allows for the Clock to be output during reset and the regular operation of the I/O pin to be overridden. When using CLKO as an output, the Clock can come from any source, including the onboard RC Oscillator. The system clock is prescaled and produced if the System Clock Prescaler is employed.

PLL

PLLs output a high-frequency clock (up to 96MHz) for use in the USB interface and High-Speed Timer module from an external low-frequency clock that they receive as input (the crystal oscillator or external clock input pin from XTAL1).

Power Management and Sleep Modes

To conserve power, applications can employ sleep modes to force the MCU to turn off inactive subsystems. Depending on the program’s needs, the user can put the AVR into one of several sleep modes. One must execute a SLEEP instruction and set the SE bit in SMCR to logic one to enter any of the five sleep modes. By selecting the appropriate bits in the SMCR Register, the SLEEP command can put the device into one of five different sleep states (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby).

Power-save Mode

When the SM2.0 bits are written to the value 011, the SLEEP instruction causes the MCU to enter the power-saving mode. This model is still available due to compatibility concerns with AT90USB64/128; however, because Asynchronous operation on Timer 2 is disabled here,  this mode is functionally equivalent to Power-down.

Conclusion

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