Part Number: LCMXO2-7000HC-4FG484I

Manufacturer: Lattice Semiconductor Corporation

Description: IC FPGA 334 I/O 484FBGA

Shipped from: Shenzhen/HK Warehouse

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Technical Specifications of LCMXO2-7000HC-4FG484I

Datasheet  LCMXO2-7000HC-4FG484I datasheet
Category Integrated Circuits (ICs)
Family Embedded – FPGAs (Field Programmable Gate Array)
Manufacturer Lattice Semiconductor Corporation
Series MachXO2
Part Status Active
Number of LABs/CLBs 858
Number of Logic Elements/Cells 6864
Total RAM Bits 245760
Number of I/O 334
Number of Gates
Voltage – Supply 2.375 V ~ 3.465 V
Mounting Type Surface Mount
Operating Temperature -40°C ~ 100°C (TJ)
Package / Case 484-BBGA
Supplier Device Package 484-FPBGA (23×23)

LCMXO2-7000HC-4FG484I Introduction

LCMXO2-7000HC-4FG484I include LUT-based, low-cost programmable logic as well as embedded block RAM (EBR), pre-engineered source synchronous I/O support,  distributed RAM, phase-locked loops (PLLs), user flash memory (UFM), advanced configuration support, including dual-boot capability, and hardened versions of frequently used functions like the SPI controller, I2 C controller, and timer/counter.

These properties enable the use of these devices in consumer and system applications that are low-cost and high-volume. The MachXO2 devices are created using a non-volatile low-power technology with a 65nm pitch. The architecture of the device enables dynamic disabling of oscillators, oscillator banks, on-chip PLLs, and low swing differential I/Os. All family members will experience low static power thanks to these capabilities that regulate static and dynamic power consumption.

Extremely low power (ZE) and high performance (HC and HE) variants of the MachXO2 devices are available. Three-speed grades—-1, -2, and -3—with -3 being the fastest—are available for extremely low-power devices. The three-speed grades for high-performance devices are also available, with -6 being the quickest. The architecture of the device enables dynamic disabling of oscillators, oscillator banks, on-chip PLLs, and low swing differential I/Os.  The external VCC supply voltage for ZE and HE devices can only be 1.2V. All three device kinds (ZE, HC, and HE) are functionally and pin-compatible with one another except for power supply voltage.

From the space-saving 2.5×2.5 mm WLCSP to the 23×23 mm fpBGA, various cutting-edge halogen-free packages are available for the MachXO2 PLDs. MachXO2 devices support density migration within the same package. Along with other important factors, Table 1-1 displays the LUT density, packaging, and I/O possibilities.

A wide range of interface standards, including LPDDR, DDR, DDR2, and 7:1 gearing for display I/Os, are supported by the pre-engineered source synchronous logic included in the MachXO2 device family.

The MachXO2 devices include bus-keeper latches,  improved I/O capabilities such as drive strength control, pull-up resistors, PCI compatibility, slew rate control, pull-down resistors, open drain outputs, and hot socketing. Controllable functions include bus-keeper, pull-up, and pull-down on a “per-pin” basis.

MachXO2 devices come with an inbuilt oscillator that the user may customize. This oscillator’s clock output can be divided by a timer or counter and used as the clock input for devices like LED controllers, keyboard scanners, and similar state machines.

Additionally, the MachXO2 devices offer secure, dependable, and flexible configurations using on-chip Flash memory. An external master can also configure these devices via the JTAG test access port or the I2 C port or by the devices themselves via external SPI Flash. Additionally, MachXO2 devices offer remote field upgrading (TransFR) and dual booting (using external Flash memory).

Modes of Operation

Each slice’s four possible operating modes are logic, ripple, RAM, and ROM. Normal Mode The LUTs in each slice in this manner are set up as 4-input combinatorial lookup tables. There are 16 possible input combinations for a LUT4. This lookup table can be programmed to produce any four input logic functions. One slice can create a LUT5 because there are two LUT4s per slice. Larger lookup tables like LUT6, LUT7, and LUT8 can be created by joining additional slices. For LUT8, more than four slices are needed.

● RAM Mode

In this mode, each LUT block in Slice 0 and 1 can be used as a 16×1-bit memory to create a 16×4-bit distributed single port RAM (SPR). Control and address signals for the memory are provided by Slice 2. One slice is used as the read-write port, and the other companion slice is used as the read-only port to create a 16×2-bit pseudo dual port RAM (PDPR) memory. Distributed memory initialization is supported by MachXO2 hardware. The Lattice design tools support the development of a wide range of memory sizes. The software will build these as necessary using distributed memory primitives that correspond to the PFU’s capabilities.


Flexible Logic Architecture

  • Six devices with 19 to 335 I/Os with LUT4s ranging from 256 to 6864

Ultra Low Power Devices

  • Advanced low-power 65 nm process.
  • Just 19 W of standby power.
  • Low swing differential I/Os that are programmable.
  • Standby mode and other alternatives for conserving energy.

Embedded and Distributed Memory

  • Up to 240 Kbits of embedded block RAM from the system.
  • 54 Kbits of Distributed RAM maximum.
  • Specialized logic for FIFO control.

On-Chip User Flash Memory

  • User Flash Memory with up to 256 Kbits.
  • A million write cycles.
  • Accessible via the JTAG, SPI, WISHBONE, and I2 C interfaces.
  • It can serve as a flash memory or a soft processor PROM.

Pre-Engineered Source Synchronous I/O

  • I/O cells have DDR registers.
  • The logic for dedicated gearing.
  • Gearing up for Display I/Os at 7:1.
  • DDRX2, DDRX4, and generic DDR.
  • DQS-compatible dedicated DDR/DDR2/LPDDR memory.

Non-volatile, Infinitely Reconfigurable

  • Instant-on; starts up in a fraction of a second.
  • Secure solution with a single chip.
  • It can be programmed using JTAG, SPI, or I2 C.
  • enables non-volatile memory to be programmed in the background.
  • Dual booting is optional and uses external SPI memory.

Enhanced System-Level Support

  • SPI, I2 C, and timer/counter are on-chip hardened functions.
  • Oscillator on-chip with an accuracy of 5%.
  • For system tracking, a unique TraceID.
  • OTP mode, or one-time programmable.
  • A solitary power source with a wide working range IEEE Spec. 1149. Boundary scan one.
  • In-system programming that complies with IEEE 1532.

Broad Range of Package Options

  • TQFP, ucBGA, caBGA, ftBGA, WLCSP, fpBGA, csBGA, QFN package options
  • Migration of density is supported.
  • Modern packaging free of halogens.


Density migration inside a single package is made possible by the MachXO2 family of materials. Additionally, the architecture guarantees a high success rate for design migration from lower-density to greater-density devices. It is frequently possible to switch a lower usage design intended for a high-density device to a lower-density device. However, the precision of the end resource use will influence each case’s likelihood of success.

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