Part Number: LMX2595RHAR

Manufacturer: Texas Instruments

Description: Phase Locked Loops

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LMX2595RHAR Description

With a frequency range of 10 MHz to 20 GHz, the LMX2595 is a high-performance wideband synthesizer that can produce any frequency in this range. Its frequency range can be altered. An integrated frequency doubler is used when working with frequencies greater than 15 GHz. A high-performance PLL with a figure of merit of -236 dBc/Hz and a high phase detection frequency can assist in attaining extremely low in-band noise and integrated jitter. This can be achieved by applying a high frequency for phase detection. The high-speed N-lack dividers of a divider have significantly decreased both the amplitude and the number of spurs. This has led to a substantial improvement. In addition, a programmable input multiplier reduces the negative effects of integer boundary spikes.

Users can synchronize the output of many devices with the aid of the LMX2595. This enables the development of applications that require a predictable delay between the input and output. The frequency ramp generator’s ability to synthesize up to two ramp segments utilizing either an automatic or a manual ramp-creating option provides the maximum degree of adjustability. This skill can be used in either direction to build a ramp. The rapid calibration approach permits frequency modifications to be accomplished in less than 20 microseconds. The LMX2595 can generate or repeat SYSREF, a signal developed for use in high-speed data converters as a low-noise clock source. This support adheres to the JESD204B standard and satisfies its requirements.

This design includes a precise delay adjustment with a 9-picosecond resolution, which can be used to compensate for the varying delay times caused by the various board traces. The output drivers housed within the LMX2595 can produce up to 7 dBm output power at 15 GHz carrier frequency. This output power is quantifiable in dB. Because the component may operate with a single 3,3-volt supply and incorporates LDOs, onboard low-noise LDOs are no longer required. This is because the element requires only one power source.

LMX2595RHAR Features

  • Output frequency: 10-MHz to 20-GHz.
  • Phase noise of -110 dBc/Hz at 100 kHz offset and 15 GHz carrier.
  • 5 GHz with 45-fs maximum jitter (100 Hz to 100 MHz).
  • variable output power

Detailed Description

The LMX2595 is a high-performance VCO and output divider built into a wideband frequency synthesizer. The VCO, which has a frequency range of 7.5 GHz to 15 GHz, may create any frequency between 10 MHz and 15 GHz when paired with the output divider. The LMX2595 also has a VCO doubler capable of generating frequencies as high as 20 GHz. To facilitate variable frequency planning, the input path includes two divisions, a multiplier and a multiplier. The multiplier allows for the depreciation of spurs by shifting the frequencies away from the boundary between integers. The phase-locked loop comprises a programmable delta-sigma modulator with a fourth-order range (PLL). It is a PLL where N is fractional.

It is uncomplicated to give small frequency increments with a precision of less than 1 Hz and a configurable 32-bit long fractional denominator. In addition, it may be used to calculate precise fractions such as 1/3, 7/1000, and many more. However, minimum N-divider values must also be considered. The SYNC pin can make the phase connection between the RFout pins  and OSCin deterministic when a deterministic or configurable phase is required. These applications may be submitted in the following formats: By dividing the VCO time by the fractional denominator, the phase can be altered in exceedingly small increments.

The ultra-fast VCO calibration was developed for use in situations and applications where the frequency must be suddenly altered or swept. The gadget can be configured to conduct ramps and chirps, or the frequency can automatically be programmed manually. JESD204B support requires the RFoutB output to generate an SYSREF differential production. Depending on the user’s settings, this differential SYSREF output can be a single pulse or a series of pulses spaced apart from the output signal’s rising edges.

The LMX2595 chip can operate with a single 3.3 V power source. Because integrated LDOs are employed to offer internal power sources, external LDOs with excellent performance are no longer necessary. The SPI interface’s digital circuitry is compatible with voltage levels ranging from 1.8 V to 3.3 V.

Feature Description

● Reference Oscillator Input

The OSCin pins provide the device with a frequency reference input in their role as inputs. The high input impedance requires AC-coupling capacitors at the plug. An XO or a CMOS clock can drive the single-ended OSCin pins. The ability to interface with high-performance system clock devices is also available with differential clock input, such as those in TI’s LMK line of clock devices. Since the OSCin signal functions as a clock in the VCO calibration process, a strong reference signal must be applied before attempting to program FCAL EN.

● Pre-R Divider (PLL_R_PRE)

The Pre-R divider is useful for decreasing the input frequency because the PLL-R divider has a maximum input frequency restriction of 250 MHz. This enables the programmable multiplier, sometimes known as the MULT, to help meet this restriction. There is no obligation to use it in that instance.

● Programmable Multiplier (MULT)

The integer boundary spurs can be avoided by adjusting the phase detector’s frequency using the MULT. The multiplier makes it easy to multiply by 3, 4, 5, 6, or 7. Be aware that the programmable multiplier reduces the PLL figure of merit compared to the doubler. However, this would only be important if there was an apparent reference and a sizable loop bandwidth.

● Post-R Divider (PLL_R)

The frequency can be further divided using the Post-R divider until it meets the phase detector frequency. When used (PLL R > 1), this divider has a lower frequency limit and a maximum input frequency of 250 MHz.

● Power-Down Modes

The LMX2595 can be powered on or off using either the CE pin or the power-down bit. For the device to be re-calibrated after being powered off and then powered on, Register R0’s FCAL EN bit must be set to high. Pushing the CE pin HIGH or setting the power-down bit to zero will achieve this.


A 24-bit shift register is used in the LMX2595’s programming. The shift register has a 7-bit address field, a 16-bit data field, and a read/write bit (MSB).

The R/W bit can take the values 0 (read) or 1 (write). The address of the internal register can be read from the range ADDRESS[6:0]. All left is the DATA[15:0] field, which consists of the final 16 bits. On the rising edge of the clock, while CSB is low, the shift register receives serial data (data is programmed MSB first). Data is moved from the data field to the chosen register bank when the CSB signal is strong.

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