LPC2368FBD100

LPC2368FBD100

Part Number: LPC2368FBD100

Manufacturer: NXP Semiconductors

Description: ARM Microcontrollers – MCU 512K FL ETHERNET USB LQFP100

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LPC2368FBD100 General Description

The LPC2364/65/66/67/68 microcontrollers are built around a real-time emulating 16-bit/32-bit ARM7TDMI-S CPU and feature up to 512 kilobytes of embedded high-speed flash memory. Execution of 32-bit code at the full clock rate is made possible via a 128-bit wide memory interface and a novel accelerator architecture. Up to 30% more performance is available than Thumb mode, making it ideal for interrupting service routines and digital signal processing algorithms. Using the alternate 16-bit Thumb mode can cut code size for space-sensitive applications by more than 30 percent with only a slight hit to performance. Any serial communication application that requires flexibility should go no farther than the LPC2364/65/66/67/68.

In addition to a 10/100 Ethernet MAC, four UARTs, two CAN channel, two Synchronous Serial Ports (SSP), an SPI interface, three I 2C-bus interfaces, and an I2S-bus interface are included. Due to their wide selection of serial communication ports, on-chip 4 MHz internal oscillator, up to 32 kB SRAM, 16 kB for Ethernet, 8 kB for USB and general-purpose applications, and 2 kB battery-powered SRAM, these devices are ideal for communications gateways and protocol converters.

Features and Benefits

  • Processor ARM7TDMI-S, operating at up to 72 MHz
  • With the ability for In-System Programming (ISP) and In-Application Programming (IAP), the on-chip flash program memory of up to 512 kB is available. Flash program memory resides on the ARM local bus for fast CPU access.
  • SRAM with 8 kB/32 kB on the ARM local bus for fast CPU access.
  • SRAM of 16 kB for the Ethernet interface. Also capable of serving as a general-purpose SRAM.
  • 8 kB SRAM for general-purpose DMA application that is also USB-accessible.
  • Execution of Ethernet, USB and on-chip flash programs can all take place simultaneously with a dual Advanced High-performance Bus (AHB) system, which ensures that none of these functions are hindered in any way. A bus bridge allows the Ethernet DMA to communicate with the other AHB subsystem.
  • The high-end vectored interrupt controller can simultaneously handle up to 32 vectored interrupts (VIC).
  • General Purpose DMA Controller on AHB that can be utilized for memory-to-memory transfers and with the Secure Digital/MultiMediaCard card port, I2S port, and SSP serial interfaces.

Functional Description

Sketch The LPC2364/65/66/67/68 microcontroller has an ARM7TDMI-S CPU that can emulate other processors, an ARM7 local bus for fast, closely coupled access to most on-chip memory, an AMBA AHB for fast peripherals, and an AMBA APB for other peripheral functions. ARM7TDMI-S processors are always set to little-endian byte order by the microcontroller.

Two AHB are implemented in the LPC2364/65/66/67/68 to ensure that the Ethernet block can function independently of any other system activity. The VIC and GPDMA controller are components of the primary AHB, often known as AHB1. The second AHB, designated AHB2, consists of the Ethernet block and a companion 16 kB SRAM. A bus bridge is also provided to facilitate Ethernet buffer expansion into off-chip memory or unused space in memory existing on AHB1, enabling the secondary AHB to act as a bus master on AHB1. In conclusion, the ARM7 core, the GPDMA sub-function, and the Ethernet sub-block are all bus masters that can use AHB1 (via the bus bridge from AHB2).

The ARM7 and the Ethernet core manage the AHB2 bus. Allotted at the very top of the 4 GB ARM memory space, the AHB peripherals take up 2 MB. Within the AHB address space, each AHB peripheral is given 16 kilobytes. There are connections to the APB for peripheral tasks that operate at lower speeds. The AHB to APB bridge acts as a connection between the two devices. Addresses in the 2 MB range, commencing at the 3.5 GB address point, are reserved for APB devices and peripherals. Within the APB address space, each APB peripheral is given 16 kilobytes.

The ARM7TDMI-S microprocessor is a high-performance, low-power, 32-bit general-purpose microprocessor. Compared to microprogrammed complex instruction set computers, the ARM architecture’s instruction set and related decode mechanism are more straightforward thanks to its foundation in RISC concepts. This ease of use allows for a compact, cheap CPU core to achieve a high instruction throughput and excellent real-time interrupt responsiveness. For continuous operation, the processor and memory systems use pipeline approaches. While one instruction is being carried out, another is being decoded and fetched from memory.

The ARM7TDMI-S processor uses a novel architectural method called Thumb, which makes it well-suited to high-volume applications with memory constraints or applications where code density is an issue.

● On-chip flash programming memory

A 128 kB, 256 kB, or 512 kB flash memory system is built into the LPC2364/65/66/67/68. Code and data alike can be stored in this RAM. Many different approaches exist for reprogramming flash memory. The serial port allows for in-system programming (UART0). This provides a lot of leeway for data storage fields and firmware upgrades, as the application program can delete and modify the flash while the application executes. The 128-bit wide flash memory utilizes pre-fetching and buffering strategies to achieve 72-MHz SRAM rates. When operating between 40 and 85 degrees Celsius, the LPC2364HBD flash can reach speeds of up to 72 MHz. At higher temperatures, it can reach speeds of up to 60 MHz.

● On-chip SRAM

The LPC2364/65/66/67/68 have either 8 kilobytes (kB) or 32 kilobytes (kB) of SRAM memory that the ARM processor can only access. Accessible in 8-bit, 16-bit, and 32-bit increments, this RAM can store code and data. Both the 8 kB SRAM utilized by the GPDMA controller or the USB device and the 16 kB SRAM block used by the Ethernet controller as a buffer can store data and code. The 2 kilobytes of read-only memory (SRAM) allocated for the RTC are strictly for storing information. The RTC SRAM relies on backup batteries to keep data even when the mains are out.

Conclusion

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