Part Number: M25P10-AVMN6TP

Manufacturer: Alliance Memory

Description: NOR Flash 1Mb 3V Serial Flash Embedded Memory

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Technical Specifications of M25P10-AVMN6TP TR

Category Integrated Circuits (ICs)
Family Memory
Manufacturer Micron Technology Inc.
Packaging Tape & Reel (TR)
Part Status Active
Format – Memory FLASH
Memory Type FLASH – NOR
Memory Size 1M (128K x 8)
Speed 50MHz
Interface SPI Serial
Voltage – Supply 2.3 V ~ 3.6 V
Operating Temperature -40°C ~ 85°C (TA)
Package / Case 8-SOIC (0.154″, 3.90mm Width)
Supplier Device Package 8-SO

M25P10-AVMN6TP Description

One megabyte’s worth of data can be stored in the M25P10A’s 125Kb x 8 serial Flash memory, and it can be accessed via any high-speed SPI-compatible bus. This device features advanced write protection mechanisms. Using the PAGE PROGRAM command, the memory can have anywhere from one to 256 bytes at a time programmed into it. It is divided into four sections, each of which has 128 pages. The width of each page is 256 bytes. Memory can be viewed as either 512 pages or 131,072 bytes, depending on how it’s used. You can use the BULK ERASE command to delete everything in the memory all at once or the SECTOR ERASE command to delete it one sector at a time.

M25P10-AVMN6TP Features

  • SPI bus-compatible serial interface
  • 1Mb Flash memory
  • 50 MHz clock frequency (maximum)
  • 3V to 3.6V single supply voltage
  • Page program (up to 256 bytes) in 1.4ms (TYP)

Operating Features

● Page Programming

Two commands are needed to program one data byte. The first command is WRITE ENABLE, which is also one byte, and the second command is a PAGE PROGRAM sequence, which is four bytes plus data. After this comes the internal PROGRAM cycle, which lasts for the allotted time. To distribute this overhead more evenly, the PAGE PROGRAM command enables the programming of up to 256 bytes at once (switching bits from 1 to 0), provided that the bytes in question are located in consecutive addresses on the same page of memory. In order to avoid having to program multiple PAGE PROGRAM sequences, each of which only contains a small number of targeted bytes, it is recommended to use the PAGE PROGRAM command to program all targeted bytes in a single sequence. This will allow timings to be optimized.

● Sector Erase, Bulk Erase

To program a single byte of data, you must execute two commands. The first command is WRITE ENABLE which requires one byte of storage space. The second command is a PAGE PROGRAM sequence and occupies four bytes in addition to the data. This is followed by the internal PROGRAM cycle, which lasts for the allocated tPP. PAGE PROGRAM is a command that enables the simultaneous programming of up to 256 bytes (switching bits from 1 to 0) by ensuring that the bytes in question are located at consecutive addresses on the same memory page. This is done to ensure that the overhead is more evenly distributed. Instead of using multiple PAGE PROGRAM sequences, each containing only a few consecutive targeted bytes, it is advised to program all consecutive targeted bytes in a single PAGE PROGRAM sequence. Because the PAGE PROGRAM command can program an entire page at once. This will allow for the optimization of timing.

● Standby Power, Active Power, and Deep Power-Down

The device is selected and operating in the ACTIVE POWER mode when chip select (S#) is in the LOW state. The device is deselected whenever S# is HIGH, but it is still possible for it to stay in the ACTIVE POWER mode until all of its internal cycles have finished (PROGRAM, ERASE, WRITE STATUS REGISTER). After that, the apparatus enters the mode known as STANDBY POWER. The consumption of the device is reduced to ICC1. Execution of the DEEP POWER-DOWN command causes the system to transition into the DEEP POWER-DOWN mode. The consumption of the device is now at ICC2, which is a lower level. The device maintains this state until the RELEASE FROM DEEP POWER-DOWN command is carried out successfully. While operating in the DEEP POWER-DOWN mode, the device disregards all WRITE, PROGRAM, and ERASE commands. When the device is not actively being used, this offers an additional software protection mechanism by safeguarding it against erroneous WRITE, PROGRAM, or ERASE operations. This occurs when the device is not in use. Please refer to the DEEP POWER DOWN command for any additional information.

● Data Protection by Protocol

Non-volatile memory is utilized in environments where excessive noise may be present. The following capabilities aid in the protection of data in these harsh environments. Power on reset and an internal timer (tPUW) can protect against accidental changes while the power supply operates outside its specifications. Before being accepted for execution, PROGRAM, ERASE and WRITE STATUS REGISTER commands are examined to ensure their clock pulse count is a multiple of eight. All data-modifying commands must be preceded by the WRITE ENABLE command, which sets the write to enable the latch (WEL) bit. In addition to its low power consumption, the DEEP POWER-DOWN mode provides additional software protection by ignoring PROGRAM and ERASE commands when the device is in this mode.


To access the status register, use the READ STATUS REGISTER command. The status register can be read even during a PROGRAM, ERASE, or WRITE STATUS REGISTER cycle. Before issuing a new command to the device during one of these cycles, it is wise to examine the write-in-progress (WIP) bit. The state register can be read continuously if necessary.


New values can be written to the status register with the help of the WRITE STATUS REGISTER command. A WRITE ENABLE command must have been issued before the WRITE STATUS REGISTER command will be recognized. The WEL bit in the write command enables the latch (WEL) to be set once the device processes the WRITE ENABLE command. To enter the WRITE STATUS REGISTER command, first set chip select (S#) to LOW, then send the command code and data byte on serial data input (DQ0). B6, b5, b4, b1, and b0 of the status register are unaffected by the WRITE STATUS REGISTER command. The values “0” are always read from status registers b6, b5, and b4. After the eighth bit of the data, the byte has been latched in, and S# must be driven HIGH. In this case, the WRITE STATUS REGISTER command is skipped.

Final Thoughts

Caution: Overloading the device beyond its specifications could result in irreparable damage. These values are stress ratings only, and it is not advised to use the device beyond the parameters outlined in the usage sections of this data sheet. Device dependability can be compromised by prolonged exposure to conditions beyond their maximum rating.

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