MCF52259CAG80 Microcontrollers

Technical Specifications of MCF52259CAG80

Datasheet	MCF52259CAG80 datasheet
Category	Integrated Circuits (ICs)
Family	Embedded – Microcontrollers
Manufacturer	Freescale Semiconductor – NXP
Series	MCF5225x
Packaging	Tray
Part Status	Active
Core Processor	Coldfire V2
Core Size	32-Bit
Speed	80MHz
Connectivity	CAN, EBI/EMI, Ethernet, I2C, QSPI, UART/USART, USB OTG
Peripherals	DMA, LVD, POR, PWM, WDT
Number of I/O	96
Program Memory Size	512KB (512K x 8)
Program Memory Type	FLASH
EEPROM Size	–
RAM Size	64K x 8
Voltage – Supply (Vcc/Vdd)	3 V ~ 3.6 V
Data Converters	A/D 8x12b
Oscillator Type	Internal
Operating Temperature	-40°C ~ 85°C (TA)
Package / Case	144-LQFP
Supplier Device Package	144-LQFP (20×20)

MCF52259CAG80 Description

The MCF52259 family of microcontrollers consists of the MCF52255, MCF52254, MCF52256, MCF52258 MCF52252, and MCF52259 devices, all of which are based on the ColdFire architecture and use a RISC instruction set. Detailed information about the MCF52259 32-bit microcontroller and its many useful features is provided here. This 32-bit device, which operates at up to 80 MHz, is based on the Version 2 ColdFire core, known for its high performance and low power consumption. Up to 512 KB of flash memory and 64 KB of static random access memory are housed on-chip, close to the CPU (SRAM). Parts of the chip itself include:

• With its Enhanced Multiply Accumulate (MAC) Unit and hardware divider, the V2 ColdFire core can generate 76 MIPS (Dhrystone 2.1) at 80 MHz operating from onboard flash memory.
• A Unit for Increasing Cryptographic Speed (CAU).
• Controller for Fast Ethernet (FEC).
• 144-pin packages support the external bus interface known as Mini-FlexBus.
• The Portable, Universal Serial Bus Computer (USBOTG).
• USB to Serial Adapter.
• Module for the CAN controller area network (FlexCAN).
• A trio of compatible synchronous and asynchronous receivers/transmitters (UARTs).
• I2C (inter-integrated circuit) bus interface modules, x 2.
• Module for a queued serial peripheral interface.
• A fast 12-bit, eight-channel ADC that can sample data in real-time.
• DMA (direct memory access) controller with four channels.
• Featuring four 32-bit timers for input capture and output comparison with Direct Memory Access (DTIM).
• Input capture/output comparison, pulse width modulation (PWM), pulse-code modulation (PCM), and pulse accumulation are all features of this four-channel general-purpose timer’s (GPT) toolbox.
• Timing circuit for pulse width modulation, with eight and four channels and a resolution of eight and sixteen bits, respectively.
• Two 16-bit timers with periodic interrupts (PITs).
• A timekeeping circuit with a 32 kilohertz (kHz) crystal is also known as an RTC.
• A timer that can act as a “watchdog” in software and can be programmed.
• Extra, clock-less watchdog timer.
• This interrupt controller can handle a total of 57 interrupts.
• The phase-locked loop and relaxation oscillator clock module operate at 8 MHz (PLL).
• Debug/access point for testing (JTAG, BDM).

V2 Core Overview

The core of the ColdFire processor, version 2, is split into two unrelated pipelines by an instruction buffer. The generation of instruction addresses and their subsequent retrieval are the responsibility of the two-stage instruction fetch pipeline (IFP). Prefetched instructions are temporarily stored in the instruction buffer while they wait to enter the operand execution pipeline, a first-in, first-out (FIFO) buffer (OEP). There are two pipeline levels in the OEP. The first stage (DSOC) is responsible for decoding instructions and choosing operands; the second stage (AGEX) executes instructions and determines effective addresses for operands, if necessary.

The V2 core utilizes the latest revision A+ of the ColdFire instruction set architecture, which includes a dedicated user stack pointer register and four additional instructions for handling bits. The enhanced multiply-accumulate (EMAC) unit is also a part of the core, and it helps the processor process signals more efficiently. With support for four 48-bit accumulators, the EMAC uses a three-stage arithmetic pipeline for 32×32-bit operations. The full complement of instructions for manipulating signed and unsigned integers of 16- and 32-bit precision, as well as signed fractional operands, are supported.  At low hardware cost, the EMAC allows digital signal processing operations to be executed within the context of a single processor.

Integrated Debug Module

System debugging is made easier using low-cost debug and emulator development tools because to the public availability of the ColdFire processor core debug interface. Access to debugging information and real-time tracing capability is available on 144-lead packages through a standard debug interface. This eliminates the need for expensive in-circuit emulators and enables full-speed debugging of the processor and system. The chip has nine programmable 32-bit registers that can be used as breakpoint resources. These registers are labeled as “address,” “data,” “PC,” and “PC mask.” These registers are accessible via either the supervisor mode programming model of the processor or the dedicated debug serial communication channel. Different combinations of address, data, and PC conditions can be defined at the single or dual level in the breakpoint registers to produce different triggers. In response to the trigger event, the CPU can be made to halt, or a debug interrupt exception can be started. The ColdFire Debug Architecture, version B+, is utilized by this tool. With the processors debug interrupt servicing options, even the most time-sensitive interrupt service routines can be executed without interrupting the emulator’s current execution. This makes sure the system keeps running even while testing and fixing bugs. The V2 debug module has both processor status (PST[3:0]) and debugs data (DDATA[3:0]) ports for use with program tracing.

This activity is defined by the CPU’s clock rate, provided by these buses, and the PSTCLK output, which contains execution status, captured operand data, and branch target addresses. The new ALLPST debug signal is included in the hardware. This signal can be used to determine whether or not the processor is halted (PST[3:0] = 1111) by being the logical AND of the processor status (PST[3:0]) signals. Only the 144-pin packages provide the full debug/trace interface. However, the ALLPST signal and the debug serial communication channel (DSI, DSO, and DSCLK) are standard on every product.

On-Chip Memories

The ColdFire core can access the 64 KB memory block provided by the dual-ported SRAM module in a single cycle. The memory block can be placed within the 4 GB address space at any 64 KB boundary.

This RAM works great as the OS stack and stores other mission-critical code or data structures.

The SRAM module’s proximity to the processor’s high-speed local bus means it can respond quickly to access requests and memory reference instructions issued by the debug module. DMA, FEC, and USB can all access the SRAM module. Because of its dual ports, SRAM is well-suited for double-buffer scheme implementations, in which the processor and a DMA device take turns using different parts of the memory to achieve peak performance.

Flash Memory

ColdFire flash modules (CFMs) are NVM modules that hook up to the fast local bus of a processor. The 512 KB of 32-bit flash memory in the CFM is generated by four banks of 64 KB16-bit flash memory arrays. These arrays can be written to and read electrically, making them a form of non-volatile memory for both code and data. The flash memory can be reprogrammed in the field without needing an external high-voltage source, making it perfect for storing programs and data in single-chip applications.

An optimized read-only memory controller that allows interleaved accesses from the 2-cycle flash memory arrays serves as the CFM’s interface to the ColdFire core. All flash memory operations, including programming, erasing and verifying, and DMA reading, are performed via backdoor mapping. The EzPort is a serial flash memory programming interface that allows the flash memory to be read, erased, and programmed by an external controller in a format compatible with most SPI bus flash memory chips.

Conclusion

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