MCP2518FDT-E/SL IC

MCP2518FDT-E/SL Device Overview

The MCP2518FD component is a CAN FD controller that is efficient in terms of cost and footprint. It is designed to integrate into any microcontroller with an accessible SPI interface. Adding a CAN FD channel to a microcontroller that does not natively support the protocol or that does not have enough CAN FD channels is a simple process. According to the requirements of ISO 11898-1:2015, the MCP2518FD chip supports the CAN frame in both the Classical format (CAN2.0B) and the CAN Flexible Data Rate (CAN FD) format.

The following enhancements were made to the MCP2518FD device:

• Low Power Mode (LPM) has been implemented to reduce leakage current to 10 A across the entire temperature range.
• The SEQ field in the Transmit Message Object and the Transmit Event FIFO Object have increased their bit count from 7 to 23.
• Added the DEVID register so that future device family members can be distinguished from one another.
• Took the step up to a saw-cut DFN package with wettable flanks.

MCP2518FDT-E/SL Features

• Serial Port CAN FD Controller Adapter for External Devices (SPI).
• Up to 1 Mbps Arbitrational Bit Rate.
• We support data rates up to 8 Mbps.
• Meets the requirements of International Standardization Organization Documentation Number 11898-1:2015 Directly Inverse First-Out (FIFO) Message Delivery
• Thirty-one FIFOs, switchable between transmit and receive modes
• There is only one transmission queue (TXQ)
• Send 32-bit time-stamped Event FIFO (TEF) messages Passage of a Message
• Automatic retransmission can be set for an unlimited number of times, for a maximum of three times, or to be disabled entirely.

Message Memory Access

Words are the focus of the access to the Message Memory (RAM) (4 bytes at a time). Reading or writing any multiple of four data bytes can be accomplished with a single instruction. After each data byte, the address is automatically increased by one position using an incrementing function. The address jumps from 0xBFF to 0x400 as it rolls over. Word spacing in Writes and Reads needs to be adjusted. It is usually presumed that the lower two bits of the address are 0, even if they aren’t. It is not possible to do reads and writes that are not aligned—the instructions for the SPI that are presented below display the various fields and their values.

SPI Commands with CRC

SPI commands with CRC are available for use when it is necessary to identify and correct bit mistakes that may occur during SPI transmission.

CRC Calculation

The CRC calculates concurrently with that of the SPI shift register.

After completing the Data portion in a CRC command, you will have access to the result of the CRC calculation. The register for CRC mismatches receives the CRC computation result. If the CRC values do not match, the CRC. The CRCERRIF flag is set.

The device known as the MCP2518FD employs the generating polynomial shown here: CRC-16/USB (0x8005) (0x8005). All single-bit and double-bit errors, faults with an odd number of bits, errors in bursts of length 16 or less, and most errors in higher lengths are caught by the CRC-16 checksum algorithm.

This enables an outstanding detection of SPI communication problems within the system, drastically decreasing the possibility of miscommunication, especially in loud surroundings. When reading or writing TX or RX Message Objects, the maximum number of available data bits are utilized. An RX Message Object has 76 bytes, also known as 608 bits if it contains 64 data in addition to 12 bytes each for its ID and time stamp. The maximum number of bits that can be included in a USB data packet is 1024. The Hamming Distance for CRC-16 ranges from 4 up to 1024 bits.

SFR READ WITH CRC – READ_CRC

The address, A[11:0], and data bytes follow the command, C[3:0] = 0b1011. After that, the data byte beginning at address A, denoted by DB[A], is shifted out, and then the data byte starting at address A+1, represented by DB[A+1]. It is possible to read any number of data bytes. After that, the CRC will be relocated (CRC[15:0]). When nCS reaches its high state, the instruction is complete.

The CRC is fed into the microcontroller at this point. The microcontroller validates the CRC. Within the MCP2518FD device, a CRC mismatch that occurs when executing a READ CRC command does not cause an interrupt to be produced. If nCS reaches high before the final byte of the CRC is shifted out, an interrupt designated as CRC Form Error will be triggered. FERRIF.

SFR WRITE WITH CRC – WRITE_CRC

The instruction begins by setting nCS to a low value. The command (C[3:0] = 0b1010), address (A[11:0], and data bytes follow the command (N[7:0]). After then, the data byte is copied to A (DB[A]) and finally to A+1 (DB[A+1]). It is possible to write any amount of data measured in bytes. The CRC will then be moved into position (CRC[15:0]). When nCS reaches its high state, the instruction is complete.

After SDI shifts the data byte, the SFR is written into the register while SCK falls. Before the check for the CRC is performed, data bytes are written to the register. After the write access, the CRC is audited for accuracy. If the CRC values do not match, an interrupt is labeled CRC.CRCERRIF will be generated. If nCS reaches high before the final byte of the CRC is shifted in, an interrupt signaling a CRC Form Error will be created with the value CRC.FERRIF.

Conclusion

A microcontroller with a spare SPI interface can quickly be outfitted with the MCP2518FD, an external CAN FD controller that is both inexpensive and compact. Therefore, a microcontroller that doesn’t have a CAN FD peripheral or enough CAN FD channels can have one added without much effort.

The MCP2518FD is compatible with the ISO11898-1:2015-specified CAN Flexible Data Rate (CAN FD) and the older Classical CAN 2.0B frame format.

Contact ICRFQ, your one-stop shop for electronic sourcing components in China, if you require further information or like to place an order for the MCP2518FDT-E/SL. We will work hard to ensure you get the best possible products at affordable prices.

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