MSP430F6736AIPNR

MSP430F6736AIPNR

Part Number: MSP430F6736AIPNR

Manufacturer: Texas Instruments

Description: IC MCU 16BIT 128KB FLASH 80LQFP

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MSP430F6736AIPNR Description

The TI MSP series of ultra-low-power microcontrollers comprises several distinct devices, each of which offers a unique collection of peripherals designed with a specific set of uses in mind. Portable measurement applications can benefit from an increased battery life because of the architecture’s optimization, which, when paired with a variety of broad low-power modes, helps achieve this goal. The hardware incorporates a robust 16-bit RISC central processing unit, 16-bit registers, and constant generators, all of which contribute to the device’s ability to run code as efficiently as possible.

The DCO enables the device to wake up from low-power settings quickly and switch into active mode under three microseconds (typical). Microcontrollers equipped with high-performance 24-bit sigma-delta ADCs (3 ADCs in MSP430F673xA and 2 ADCs in MSP430F672xA), four eUSCIs (three eUSCI A modules and one eUSCI B module), a 10-bit ADC, four 16-bit timers, a DMA module, an RTC module with alarm capabilities, a hardware multiplier, and an LCD driver with integrated

Detailed Description

Overview

The MSP430F673xA and MSP430F673xA microcontrollers both have four enhanced universal serial communication interfaces (eUSCI) (three eUSCI A modules and one eUSCI B module), four 16-bit timers, a DMA module, and an RTC module with alarm capabilities.

● CPU

The MSP430 central processing unit (CPU) utilizes a 16-bit RISC architecture that is largely hidden from the application. Except for the instructions that control the program flow, all operations are carried out as register operations in conjunction with seven different addressing modes for the source operand and four different addressing modes for the destination operand. The central processing unit (CPU) includes sixteen registers, each of which reduces the amount of time needed to execute an instruction. The time required to carry out a register-to-register instruction corresponds to one cycle of the central processing unit’s clock. From R0 to R3, the registers handle the program counter, stack pointer, status register, and constant generator.

● Instruction Set

The initial 51 instructions are included in the instruction set, along with three different instruction formats, seven additional address modes, and additional instructions to cover the increased address range. Every instruction is capable of performing operations on word data as well as byte data.

● Bootloader (BSL)

Users can use various serial interfaces to write programs that can be stored in the RAM or flash memory utilizing the BSL. A password that the user chooses guards the memory of the device while it is accessed through the BSL. A particular entry sequence must be performed on the RST/NMI/SBWTDIO and TEST/SBWTCK pins to gain access to BSL.

● Peripherals

The central processing unit (CPU) is connected to the computer’s peripherals by data, address, and control buses. All of the instructions can be used to deal with the peripherals.

● Oscillator and System Clock

The Unified Clock System module supports a watch crystal oscillator with a frequency of 32768 Hz. In addition, the module can use its own very low power and low frequency (VLO) oscillator, internally trimmed low frequency (REFO), and digitally controlled oscillator (DCO).

The UCS module has been developed to fulfill the requirements of a low total system cost and power consumption. The digital frequency-locked loop (FLL) hardware included in the UCS module works in concert with a digital modulator to maintain the frequency of the DCO at a programmable multiple of the FLL reference frequency that has been specified. The clock is stabilized in three microseconds thanks to the device’s built-in DCO, which also allows for a quick turn-on (typical).

● Power-Management Module (PMM)

A voltage regulator included in the PMM provides the device with the core voltage. This regulator also has configurable output levels, allowing power optimization. Circuitry for supply voltage supervisor (SVS) and supply voltage monitoring (SVM) are also included in the PMM, in addition to brownout prevention. During the power-on and power-off phases of the device’s operation, the brownout circuit is activated to send the correct internal reset signal. Both supply voltage supervision (in which the device is immediately reset) and supply voltage monitoring are supported by the SVS/SVM circuitry, which detects if the supply voltage drops below a user-selectable level (the device is not automatically reset). Both SVS and SVM can be obtained from the primary supply as well as the core supply.

● Auxiliary Supply System

When the primary supply fails, the device can still be operated using the auxiliary supplies thanks to the auxiliary supply system’s provision of this capability. Two auxiliary power supplies are supported; their designations are AUXVCC1 and AUXVCC2. This module allows for automated and manual switching between the primary and auxiliary supplies while preserving all functionality.

It allows the monitoring of primary and auxiliary supplies depending on predetermined thresholds. Either the primary supply or AUXVCC1 can power up the device; whichever of the two supplies has a higher voltage will be used. ADC10 A is utilized to enable the auxiliary supply system’s internal monitoring of voltage levels on the primary and auxiliary supplies. Additionally, this module includes a straightforward charger for the auxiliary power supply.

● Backup Subsystem

The Backup subsystem makes use of an independent power source designated as AUXVCC3. The low-frequency oscillator (XT1), the RTC module, and the backup RAM are all components of this subsystem. During the LPM3.5 maintenance release, the Backup subsystem will continue to provide the same level of functionality. If the user turns off the high-side safety ventilation system, the CPU cannot access the Backup subsystem module registers. To deactivate the low-frequency oscillator (XT1) in LPM4, it is essential to keep the high-side SVS enabled with SVSHMD = 1 and SVSMHACE = 0. This can be done by entering those values into the corresponding registers.

Conclusion

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