RT9610BZQW MOSFET Driver

RT9610BZQW Description

In synchronous-rectified buck converter topologies, the RT9610A/B is a high-frequency dual MOSFET driver, where each MOSFET is responsible for driving a single-power N-MOSFET. Because of its high efficiency and top-notch thermal performance, it is ideal for mobile computing applications. In conjunction with Richtek’s other series of multi-phase Buck PWM controllers, this driver offers a full-featured solution for the core voltage regulator of modern microprocessors.

The drivers have a fast rise/fall time and a short propagation delay, allowing them to drive a 3nF load successfully. This device can use just one external capacitor to implement bootstrapping on the upper gates. This simplifies the implementation and allows for more efficient and less expensive N-MOSFETs to boost performance. To prevent the two MOSFETs from conducting simultaneously, adaptive shoot-through protection has been built in. The RT9610A/B is offered in the 3×3 WQFN-8L package and the 2×2 WDFN-8L package.

RT9610BZQW Feature

● Two N-MOSFETs power it.

● Shoot-Through Protection that Adapts.

● 4A Sink Current Capability, 0.5 On-Resistance.

● High Switching Frequency Supported

● Tri-State PWM Input for Shutting Down the Power Stage.

● Disable Function is output.

● Built-in boost switch.

● Low Bias Current Supply.

● Integrated POR feature for VCC.

● 8-Lead WDFN Package, small.

● Free of halogens and RoHS compliant.

RT9610BZQW Applications

• Core Voltage Supplies for Intel® / AMD® Mobile Microprocessors
• High-Frequency Low Profile DC-DC Converters
• High Current Low Output Voltage DC-DC Converters
• High Input Voltage DC-DC Converters

Operation

● POR (Power On Reset)

The POR block monitors the supply voltage at the VCC terminal. The POR pin output voltage (POR output) is high when the VCC pin voltage is greater than the POR rising threshold. When VCC is below the POR rising threshold, POR output is low.

When the POR pin is at a high voltage, the PWM input voltage can modulate UGATE and LGATE. When the voltage on the POR pin is low, UGATE and LGATE are both forced low.

● Tri-State Detect

UGATE and LGATE can be modulated by PWM input when the POR output and EN pin voltages are high. Input PWM levels can be set to high (the default), low (half-scale), or off (shutdown). The UGATE and LGATE outputs will be low if the PWM input is within the shutdown window. UGATE is high, and LGATE is low when the PWM input is above the rising threshold. When the PWM input is below the falling threshold, the UGATE is low, and the LGATE is high.

● Control Logic

By checking for (UGATE – PHASE) voltages below 1.1V or PHASE voltages below 2V, the control logic block can determine if the high-side MOSFET has been disabled. Turning on the low-side MOSFET necessitates effectively turning off the high-side MOSFET to avoid gate-drive overlap when the UGATE is pulled low, and the LGATE is pulled high.

● Shoot-Through Protection

When both the high and low-side MOSFETs are disabled, the dead time is implemented by a shoot-through protection block. The shoot-through protection block prevents the simultaneous activation of the high- and low-side MOSFETs. As a result, the MOSFETs on the high and low sides of the circuit are protected from each other.

Application Information

● Supply Voltage and Power On Reset

High- and low-side N-MOSFETs can be driven by the RT9610A/B with the help of a pulse-width-modulated (PWM) control signal that is input from the outside. Power the RT9610A/B by connecting 5V to VCC. It is suggested that a ceramic capacitor of at least 1F be used to filter out the power supply. To avoid damaging the IC, you should put the bypass capacitor close to it. To keep tabs on the VCC supply voltage, the power on reset (POR) circuit is constantly watching that pin. The controller is reset and readied for operation if VCC rises above the POR increasing threshold voltage. Before VCC rises above the POR falling threshold, UGATE and LGATE are kept at low levels.

● Enable and Disable

A sequence control EN pin is available on the RT9610A/B. In response to an increase in the EN pin above the VENH trip point, the RT9610A/B initiates a fresh initialization round and responds to PWM commands regarding UGATE and LGATE operation. The RT9610A/B powers down and maintains a low state for UGATE and LGATE when the EN pin falls below the VENL trip point.

● Three-State PWM Input

The PWM signal takes over once the system has been initialized. To prevent a shoot-through current, the PWM signal first drives the LGATE signal low before allowing the UGATE signal to go high at a non-overlapping time. In contrast, UGATE is initially driven low by the decaying PWM signal. The LGATE signal can go high once the UGATE or PHASE signal falls below a threshold.

● Non-overlap Control

By keeping an eye on the voltage at the PHASE node and the high side gate drive, the non-overlap circuit ensures that the UGATE pull low and the LGATE pull high never overlap (UGATE-PHASE). If the PWM input signal drops to a low level, UGATE will start to pull low (after propagation delay). The monitored (UGATEPHASE) voltages must drop below 1.1V, or the phase voltage must be below 2V before the LGATE can pull high, as the non-overlap protection circuit ensures this. If the monitored voltages drop below the setpoint, LGATE will go high. To prevent UGATE from being high when LGATE pulls high, the non-overlap protection circuit waits for the PHASE pin and high side gate drive voltages to drop below their threshold. The LGATE voltage is monitored by the non-overlap circuit, which also prevents the overlap of the gate drives during LGATE pull low and UGATE pull high. Increasing UGATE when LGATE falls to 1.1V or more is acceptable.

Final thoughts

The UGATE pull low, and the LGATE pull high are never superimposed thanks to the non-overlap circuit, which monitors the voltage at the PHASE node and the high side gate drive (UGATE-PHASE). If the PWM input signal weakens, UGATE will begin a low-impedance pull-down (after propagation delay). For the LGATE to pull high, the non-overlap protection circuit must verify that the monitored (UGATEPHASE) voltages are less than 1.1V or that the phase voltage is less than 2V.

As monitored voltages fall below the threshold, LGATE will go high. The non-overlap protection circuit waits for the PHASE pin and high side gate drive voltages to fall below their threshold, preventing UGATE from being high when LGATE pulls high. The non-overlap circuit not only keeps the gate drives from overlapping during LGATE pull low and UGATE pull high, but it also keeps an eye on the LGATE voltage. If LGATE drops to 1.1V or less, it is acceptable for UGATE to be high.

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