Part Number: STM32G030K6T6

Manufacturer: STMicroelectronics

Description: ARM Microcontrollers – MCU Mainstream Value-Line Arm Cortex-M0+ MCU 32 Kbytes of Flash 8 Kbytes RAM, 64 MHz

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STM32G030K6T6 Description

The 32-bit RISC Arm® Cortex®-M0+ CPU that powers the STM32G030x6/x8 mainstream microcontrollers operates at speeds of up to 64 MHz. They are equipped with IoT solutions and can be used in a wide range of consumer, industrial, and appliance contexts thanks to their advanced level of integration. The hardware includes a DMA, high-speed embedded memories,  numerous system features, enhanced I/Os, peripherals, a memory protection unit (MPU), and up to 64 KB of read-write-protected Flash programmable memory.

STM32G030K6T6 Features

  • Arm® 32-bit Cortex®-M0+ CPU, operating at a maximum frequency of 64 MHz.
  • working temperature range: -40°C to 85°C.
  • Calculation unit for CRC.
  • Flexible 5-channel DMA controller mapping.
  • 8 clocks Four 16-bit general-purpose, two watchdogs, four 16-bit for advanced motor control, and a SysTick timer.
  • Calendar RTC with alert and recurrent standby/stop wakeups.

Functional Overview

The Cortex-M0+ is a low-cost 32-bit Arm Cortex processor suitable for numerous embedded uses. It provides many advantages to developers, including:

  • As easy to understand and work with structure.
  • Efficiency and low power consumption are hallmarks of ultra-low power operation.
  • Superior compactness of code.
  • A reliable and fast way to handle interruptions when they occur.
  • The ability to work with more advanced processor families, such as the Cortex-M.
  • The stability of the platform’s security is thanks to the Memory Protection Unit (MPU).

The Cortex-M0+ processor has a 2-stage pipeline Von Neumann design and is based on a 32-bit core that is exceptionally efficient in terms of size and power consumption. A single-cycle multiplier and other cutting-edge computing devices are made possible by the processor’s small yet powerful instruction set, highly optimized design, and exceptional energy efficiency. The Cortex-M0+ CPU provides the more excellent performance anticipated of a contemporary 32-bit architecture while offering a higher code density than other 8-bit and 16-bit microcontrollers. Due to the inbuilt Arm core, the STM32G030x6/x8 devices are compatible with Arm software and tools.

Memory Protection Unit

The memory protection unit (MPU) is used to manage CPU access to memory to prevent accidental corruption of memory or resources being used by any other current job. When it’s crucial to protect certified or vital code from the inaccuracies of other activities, the MPU comes in handy. Most of the time, RTOSs are in charge of it (in the real-time operating system). If a piece of software attempts to access a section of memory that the MPU has specifically marked as off-limits, the RTOS will be able to detect this and take appropriate action. During operation in a real-time operating system (RTOS), the kernel can dynamically change the MPU area setting by the running process. The MPU is unnecessary and can be disabled in unnecessary programs.

Embedded SRAM

Parity-enabled static random-access memory (SRAM) in STM32G030x6/x8 devices is 8 kilobytes in size. Using a hardware parity check, memory data mistakes can be found and fixed, improving the software’s reliability. The memory can be read from and written to at full speed of the processing unit with no wait states.

Cyclic redundancy check calculation unit

If you need a CRC code, you can adjust the size and value of the generator polynomial that the CRC (cyclic redundancy check) computation unit uses. Validating data integrity during transmission or storage is just one usage for CRC-based approaches. Within the confines of EN/IEC 60335-1, they provide a method of ensuring the reliability of Flash memory. The CRC calculation unit aids in generating a software signature at runtime, which can then be compared to a reference signature generated at link time and saved in a specific memory address.

Power supply supervisor

All power modes are supported via the device’s built-in power-on/power-down (POR/PDR) reset, which initiates when power is applied and disables when power is removed. When the supply voltage drops below the VPOR/PDR threshold, the device remains reset without the requirement for an external reset circuit.

Voltage regulator

Two internal linear voltage regulators, the primary regulator (MR) and the low-power regulator, power much of the device’s digital circuitry (LPR). Both the active and inactive modes of the MR are functional. The LPR is turned on in the Stop, Low-power Sleep, and Low-power Run modes. When in Standby mode, both regulators are turned off, and their outputs are set to a high-impedance condition, which effectively lowers their current consumption to nearly nothing.

Reset mode

To conserve power, Schmitt triggers on I/Os are disabled before and after a reset. When the reset source is internal, the NRST pin’s built-in pull-up resistor is deactivated, too.

VBAT operation

The VBAT power domain consists of low-power elements such as the real-time clock (RTC), low-frequency stable oscillator (LFE), and backup registers. When in VBAT mode, the RTC domain is powered by the VBAT pin. A supercapacitor or an external battery are suitable alternatives for this power source. Two tamper-proof pins are included for additional security. The RTC system can alternatively be powered by the VDD/VDDA pin. To keep the RTC domain’s supply voltage (VBAT) within safe operating ranges, an internal voltage supervisor allows for automatic switching between VDD and voltage from the VBAT pin. The VDD/VDDA pin powers the RTC domain if both are functional. An internal circuit will be turned on to charge the battery connected to the VBAT pin if the VDD voltage is suitable.

Interconnect of peripherals

There are direct connections between several different peripherals. This enables peripherals to communicate without the need for the central processing unit (CPU), reducing the load on the power supply. Further, fast and reliable latency is possible because of these hardware connections. These connections may use Run, Sleep, or Stop modes as necessary for the connected peripherals.

General-purpose inputs/outputs (GPIOs)

The software allows for the GPIO pins to be set up in a variety of different ways, including as outputs (push-pull or open-drain), inputs (with or without pull-up or pull-down), and additional pins (AF). Generally, purpose, input/output (GPIO) pins serve multiple digital or analog purposes.

This unique I/O configuration can be secured to prevent unwanted changes to the I/O control registers.

DMA request multiplexer

The DMAMUX request multiplexer allows a DMA request line to be sent from the peripherals to the DMA controller. Each channel selects a unique DMA request line independently or in sync with events from its DMAMUX synchronization inputs. DMAMUX can also produce DMA requests based on events on its input trigger signals, which can be configured.

Interruptions and happenings The system is adaptable in the face of exceptions or events that halt the standard processing of a linear program. The Cortex-M0+ processing core, the nested vectored interrupt controller (NVIC), and the extended interrupt/event controller all play a role in handling exceptions (EXTI). Exceptions include core-internal events like a division by zero and core-external events like logical level shifts on physical lines. When an exception occurs, the normal flow of the program is temporarily halted so that an interrupt service routine (ISR) can be executed.

When an application is interrupted by hardware, the processor context is stacked and then unstacked when the application is resumed. The software can conserve resources, including time, code, and energy, during interrupted service procedures, by avoiding the need for stacking and unstacking of context (ISRs). Since load-multiple and store-multiple operations can be paused and resumed, the device is significantly more reactive when handling errors.


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