TLE8242-2L Controllers

TLE8242-2L General Description

By setting the proper CM bit in SPI message #1, each channel can operate in either the direct PWM mode or the constant current manner, depending on how the channel is configured.

Summary of Features

• Low side constant current control pre-driver integrated circuit
• Four independent channels
• Output current programmable with 11-bit resolution
• Current range = 0 to 1.2A (typ.) with a 0.2Ohm sense resistor
• Resolution = 0.78125 mA/bit (typ.) with a 0.2Ohm
• sense resistor
• +/- 2% full-scale error over temperature when autozero is used
• Programmable PWM frequency via SPI from approximately 50 Hz to 4 kHz (typ.)
• Interface and Control
• 32 Bit SPI (Serial Peripheral Interface) – Slave only
• Active low RESET_B pin resets internal registers to their default state and disables all channels.
• 0V and 3.3V logic compatible I/O
• Protection
• Over-current shutdown – monitored at POSx pin.
• Programmable over-current threshold
• Programmable over-current delay time
• Programmable over-current retry time
• Battery pin (BAT) overvoltage shutdown

Potential Applications

• Other constant current solenoids
• Idle Air Control
• Exhaust Gas Recirculation
• Vapour Management Valve
• Suspension Control

Benefits

• Sense resistor can be scaled to expand solenoid current range above 1.2A
• Minimal protection circuitry can be added to use the TLE8242-2L in 24V applications (commercial vehicles)
• The current profile detection feature can be used to determine the movement of the solenoid armature

Functional Description and Electrical Characteristics

Availability and Citation A reset button is available upon turning on the device. When the voltage on V5A1, V5A2, V5A3, and V5D falls below their reset thresholds, the channels will be disabled, and the internal registers will be reset to their default values. Power and ground for the digital logic blocks are connected to the V5D and GND D pins, respectively. There is a lot of high-frequency energy flowing through these pins. Decoupling with ceramic capacitors and careful PCB architecture is essential to achieve high EMC performance.

The power and ground for the analog circuitry are connected to the V5A1, V5A2, and V5A3 pins and the GND A pin. The SPI output (SO) and the pull-up voltages for CS B and RESET The V SIGNAL pin supplies b. Connect V SIGNAL to the microcontroller’s output power (3.3V or 5.0V). Overvoltage faults can be detected through the BAT input pin. It is not possible to connect a power source to this terminal. To prevent damage from voltage spikes, a resistor should be wired in series between this pin and the solenoid’s power source.

● Input / Output

Every digital input can work with either 3.3 V or 5 V I/O logic levels. The V SIGNAL pin is the location of the supply voltage for the SPI output SO. When the device is not attached, all digital inputs are brought to a known state by a weak current source or sink located within. Nevertheless, unused digital input pins should be linked to ground or V SIGNAL (depending on the desired functionality) using an external connection or a resistor. The V SIGNAL pin is the one that supplies all of the input pins’ feeble internal current sources. A low-level active input signal can be received on the RESET B pin. Setting the proper CM bit in SPI message #1 allows you to switch between direct PWM and constant current modes for each channel.

An external source must keep the device in its reset state until all the power supplies have reached their steady state. The integrated circuit powers on and resets if the input voltages V5D, V5A1, V5A2, or V5A3 fall below the Undervoltage reset criterion. For the device to function normally, the ENABLE pin, an active high input pin, must be kept in the high state at all times. Depending on how the enabling behavior of the channel was set using SPI Message #10 when this pin is kept low, all channels are switched off or will remain in the last state. When the ENABLE pin is low, the circumstance that occurs by default is that all of the channels are disabled. The primary clock input for the device is located on the CLK pin. The input thresholds are adjustable to accommodate logic levels of both 3.3 V and 5.0 V. There is no need for synchronization between the clock signal linked to the CLK pin and the SPI (SCK) signal. This clock input generates all of the TLE8242’s internal clock signals, including PWM signals, A/D sampling, diagnostics, etc. In addition, this clock is necessary for the device to receive and reply to SPI signals.

● Diagnostics

The TLE8242 has diagnostic features that work in both on- and off-state modes. Driving the OUTx pin high activates the on-state diagnostics while driving it low activates the off-state diagnostics. Once a fault has been found, the open drain FAULT pin on the IC can be driven high. When an error is discovered, this pin can reset the microcontroller. Setting the fault mask register in SPI message #1 will prevent some faults from triggering the FAULT pin. After a malfunction is identified, it is stored in the appropriate fault register and latched.

Fault registers are accessible to the microcontroller via SPI messages 4, 5, and 19. The Generic Flag Bits register will latch an RB L bit whenever the RESET B line goes from high to low. Once this register is read via the SPI, it is immediately cleared, and the RB L bit will remain unset until the RESET B pin becomes high again. The Generic Flag Bits register’s EN L bit is latched if the voltage on the ENABLE pin is very low. Returning the ENABLE pin to its usual high condition and sending SPI message #19 to the Generic Flag Bits register will reset the ENL bit. A master clock signal is provided to the pin CLK, and the on-state and off-state diagnostic delay times are calculated using a programmable divider from that signal. The DIAG TMR bits of the first SPI message can be used to customize the divider’s settings.

Conclusion

Setting the proper CM bit in SPI message #1 allows you to switch between direct PWM and constant current modes for each channel.

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