Part Number: TPS386000RGPR

Manufacturer: Texas Instruments

Description: Supervisory Circuits Quad Supply Vltg Sup

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Technical Specifications of TPS386000RGPR

Datasheet  TPS386000RGPR datasheet
Category Integrated Circuits (ICs)
Family PMIC – Supervisors
Manufacturer Texas Instruments
Packaging Tape & Reel (TR)
Part Status Active
Type Multi-Voltage Supervisor
Number of Voltages Monitored 4
Output Open Drain or Open Collector
Reset Active Low
Reset Timeout Adjustable/Selectable
Voltage – Threshold Adjustable/Selectable
Operating Temperature -40°C ~ 125°C (TJ)
Mounting Type Surface Mount
Package / Case 20-VFQFN Exposed Pad
Supplier Device Package 20-QFN (4×4)

TPS386000RGPR Description

The supply voltage supervisors (SVSs) in the TPS3860x0 family have an average threshold accuracy of 0.25% and can monitor four power rails with a voltage greater than 0.4 V as well as one power rail with a voltage less than 0.4 V. Additionally, this family of SVSs can monitor one power rail with a voltage less than 0.4 V. (including negative voltage). When the SENSEm input voltage falls below the predetermined threshold, each of the four supervisory circuits (SVS-n) will assert either the RESETn or RESETn output signal, depending on which of the two it is—modifying the threshold of each SVS-n (where n = 1, 2, 3, 4 and m = 1, 2, 3, 4L, 4H, respectively) can be done with the help of resistors that are located outside the system. Before releasing RESETn or RESETn, the SVS-n in each device has a delay that the user can adjust. This delay is adjustable.

Through the CTn pin connection, the delay time can be altered independently for each SVS, and its duration can range anywhere from 1.4 milliseconds to ten seconds. Only the SVS-1 has an active-low manual reset (MR) input; a piece of logic-low information to MR asserts RESET1 or RESET1. Only the SVS-1 has an active-low manual reset (MR) input. The SVS-4 utilizes two comparators to perform its threshold window monitoring. The additional comparator can be set up to monitor the negative voltage in conjunction with a voltage reference output VREF, allowing it to function as a fifth SVS. The TPS3860x0 is offered in a compact packaging option called VQFN-20. It has a side measurement of only 4 millimetres and an average quiescent current of 11 microamperes.

TPS386000RGPR Features

  • Delay Time Adjustment: 1.4 ms to 10 s.
  • Accuracy at the threshold: 0.25% Usually.
  • 11 Typical Very Low Quiescent Amps.
  • With Dedicated Output, a watchdog timer
  • Consistent Output During Power Up.
  • TPS386000: WDO with Open-Drain RESET.
  • Push-Pull RESETn and WDO are part of TPS386040.
  • 20-Pin VQFN, 4-mm 4-mm package.

Feature Description


The multi-channel supervisory family of devices known as the TPS3860x0 incorporates four entire SVS function sets onto a single integrated circuit (IC), a watchdog timer, a window comparator, and negative voltage sensing. TPS3808, a single-channel supervisory device series, served as the basis for designing each SVS channel.

● Manual Reset

It is possible to reset the device in response to a logic signal from an external source by using the manual reset (MR) input. This signal could come from another processor, a logic circuit, or a discrete sensor. The RESET1 or RESET1 pin, which is supposed to be attached to the processor, serves as the principal source of the reset signal (s). This is because MR is attached to SVS-1. When the logic level at MR is low, either RESET1 or RESET1 will be asserted.

RESET1 or RESET1 is released after a delay that the user selects after MR has recovered to a tolerable high condition and SENSE1 has risen beyond its reset threshold. This occurs when RESET1 or RESET1 is released. Compared to the TPS3808 series, the TPS3860x0 series clearly lacks an internal pull-up resistor coupled to MR and VDD. This is evident when comparing the two series. Using wired-OR, numerous NMOS transistors, and a pullup resistor fed into a single MR pin, various logic signals can be aggregated into a single signal and used to govern the MR function. This can be accomplished by feeding the aggregated signal into a single MR pin.

● Watchdog Timer

A watchdog timer that includes a dedicated watchdog error output, also known as a WDO or WDO, is made available by the TPS3860x0. Application board designers are given the ability to quickly detect and resolve the hang-up status of a processor through the utilization of the WDO or WDO output. The watchdog timer function of the device is also connected to SVS-1, just like MR’s watchdog timer function.

● Reset Output

In a typical application for the TPS3860x0, the RESETn or RESETn outputs are connected to the reset input of a processor (such as a DSP, CPU, FPGA, or ASIC, amongst others), or they are connected to the enable input of a voltage regulator (DC-DC, LDO, and so forth). The TPS386000 includes reset outputs that have open-drain connections. Pullup resistors must be utilized to maintain the high state of these lines regardless of whether or not the RESET signal is being asserted. Connecting the RESETn or RESETn output nodes to the other devices at the appropriate interface voltage levels is possible. This is achieved by clicking pullup resistors to the correct voltage rails (up to 6.5 V).

To guarantee the output transistors’ proper functioning and avoid any potential hazards, the pullup resistor’s value shouldn’t be lower than 10 k. Any combination of RESETn can be merged into one logic signal using wired-OR logic. This allows for greater flexibility. Push-pull reset outputs are available from the TPS386040. The VDD’s voltage controls the logic high level produced by the outputs. Because of the way this configuration is set up, pullup resistors are optional, which frees up some space on the circuit board. Nevertheless, every level of the interface’s logic ought to be investigated. Every RESETn or RESETn connection must be compatible with the VDD logic level.


Recommendations and Suggestions Regarding the Power Supply the TPS386000 can function with an input supply voltage ranging from 1.8 V to 6.5 V. According to the recommendations made by TI, the GND node and the VDD pin should be positioned close to one another, and a capacitor with 0.1 microfarads of capacitance should be utilized. This power supply must maintain a voltage of 1.8 V or above during operation to prevent the internal UVLO circuit from entering reset mode and causing the device to malfunction. If it does not, the device will not function properly.

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