LPC1788FBD208

LPC1788FBD208

Part Number: LPC1788FBD208

Manufacturer: NXP USA Inc

Description: IC MCU 32BIT 512KB FLASH 208LQFP

Shipped from: Shenzhen/HK Warehouse

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LPC1788FBD208 Description

The LPC178x/7x is a microcontroller based on the ARM Cortex-M3 architecture, making it suitable for low-power, highly integrated embedded applications. The ARM Cortex-M3 is a next-gen core that outperforms the ARM7az at the same clock rate and provides other system improvements like updated debug features and tighter integration of support blocks. The ARM Cortex-M3 central processing unit (CPU) features a three-stage pipeline and a Harvard architecture with local instruction and data buses that are isolated from one another and a third bus with slightly reduced performance for use by peripherals.

The ARM Cortex-M3 central processing unit has a speculative branching capability and a prefetch unit built right in. To maximize performance when running code stored in a flash, the LPC178x/7x includes a dedicated flash memory accelerator. The LPC178x/7x can reach a maximum CPU speed of 120 MHz. The LPC178x/7x has a maximum of 512 kilobytes of flash program memory, 96 kilobytes of SRAM data memory, 4032 bytes of EEPROM data memory, an LCD (LPC178x only), Ethernet, USB Device/Host/OTG, five UARTs,  three SSP controllers,  a General Purpose DMA controller, three I2C-bus interfaces, and one eight-channel 12-bit ADC and one 10-bit DAC. The LPC178x/7x pinout is backward-compatible with the LPC24xx and LPC23xx in terms of pin functions.

Functional Description

● Architectural overview

The ARM Cortex-M3 has three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. Tightly Coupled Memory (TCM) interfaces use the I-code and D-code core buses in much the same way. The I-code core bus is the primary mechanism for instruction fetch, and the D-code core bus is used for data access (D-code). Using two core buses enables simultaneous operation when concurrent operations are directed at different devices.

The LPC178x/7x use a multilayer AHB matrix to connect ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by permitting simultaneous access by multiple bus masters to peripherals on different slave ports of the matrix.

● On-chip flash program memory

The LPC178x/7x has up to 512 kilobytes of flash memory that can be programmed. To maximize the performance of the two extremely fast AHB-Lite buses, a new two-port flash accelerator was designed.

● On-chip SRAM

The LPC178x/7x have up to 96 kB of on-chip static RAM for storing information. There is a primary 64 kB SRAM that the CPU and DMA controller can access via a faster bus, and there can be up to two more SRAM blocks, each measuring 16 kB, located on a dedicated slave port on the AHB multilayer matrix. This design distributes CPU and DMA accesses across three independent RAMs for simultaneous access.

● Memory Protection Unit (MPU)

The Memory Protection Unit (MPU) available on the LPC178x/7x can increase the dependability of an embedded system by safeguarding sensitive information generated by the user’s program. The MPU partitions processing tasks by blocking data access, defining memory regions as read-only, and detecting random memory accesses that could crash the system. The MPU partitions memory into secure areas and blocks unauthorized access to these sections. Each MPU’s eight supported regions can be further subdivided into up to eight smaller subregions. The Memory Management Fault exception will occur if an attempt is made to access a memory location that is not defined in the MPU regions or permitted by the region setting.

● Pulse Width Modulator (PWM)

There are two regular PWMs on board the LPC178x/7x. Although only the PWM function is pinned out on the LPC178x/7x, it is based on the standard Timer block and inherits all of its features. Based on seven match registers, the timer can count cycles of the system-derived clock and toggle pins, trigger interrupts, or do other things at predetermined intervals. Aside from these capabilities, the PWM feature is also available and operates based on match register events. Because the PWM’s rising and falling edge locations can be adjusted independently, it can be used in broader contexts. For instance, controlling a multi-phase motor requires a PWM controller with three independent outputs, each of which can have its pulse width and position.

A single edge-controlled PWM output can be generated using just two match registers. The PWM cycle rate is governed by a single match register (PWMMR0), which resets the counter after each match. The other matching register manages the PWM edge position. Since the repetition rate is the same for all PWM outputs, additional single-edge controlled PWM outputs only need one match register. When a PWMMR0 match occurs, all PWM outputs controlled by a single edge will start each cycle with a rising edge.

You can control both edges of a PWM signal by using three match registers. The PWM cycle rate is adjusted via the PWMMR0 match register. The other match registers manage the two PWM edge positions. Since the repetition rate is constant for all PWM outputs, adding double-edge controlled PWM outputs only requires two match registers per output. The rising and falling edges of PWM outputs can be independently owned using two separate match registers. This allows for both positive-going and negative-going PWM pulses (when the rising edge precedes the falling edge) (when the falling edge occurs before the rising edge).

Final Thoughts

The LPC1788FBD208,551 microcontroller by NXP Semiconductors is an essential part of any electronic system because it can be programmed to perform any task. The temperature range that this microcontroller can work in is between -40 and 85 degrees Celsius. Its maximum clock speed is 120 MHz. The typical supply voltage for this device is 3.3 V. It requires a power supply between 2.4 V and 3.6 V to function correctly. It has 512 kilobytes of programmable flash memory. The processor inside this is 32 bits. The ARM Cortex M3 is the device’s central processor. The resolution in the ADC is 12.

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