STM32F091CCT6

STM32F091CCT6

Part Number: STM32F091CCT6

Manufacturer: STMicroelectronics

Description: IC MCU 32BIT 256KB FLASH 48LQFP

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STM32F091CCT6 Description

The STM32F091xB/xC microcontrollers feature fast embedded memories (up to 256 Kbytes of Flash memory and 32 Kbytes of SRAM), an extensive array of enhanced peripherals, and high-performance ARM®Cortex®-M0 32-bit RISC cores operating at up to 48 MHz. The device has eight USARTs, an HDMI CEC, a CAN, a 12-bit ADC, a 12-bit DAC with two channels, seven 16-bit timers, a 32-bit timer, and an advanced-control PWM timer.

Microcontrollers from STM32F091xB/xC work from a 2.0 to 3.6 V supply and are functional in temperatures ranging from -40 to +85 °C and -40 to +105 °C, respectively. Low-power application development is made possible by a variety of power-saving modes.

Devices in seven different packages, with pin counts ranging from 48 to 100, make up the STM32F091xB/xC microcontrollers; a dying form is also available on demand. Different sets of accessories are provided with various devices.

The STM32F091xB/xC microcontrollers’ flexible design and rich set of features make them ideal for use in a wide variety of devices and settings, including but not limited to: industrial applications; PLCs; inverters; printers; scanners; alarm systems; video intercoms; HVACs; and handheld devices; audio/video receivers and digital televisions; PC peripherals; gaming and GPS platforms; and home automation and security systems.

Functional Overview

● ARM®-Cortex®-M0 core

ARM has developed the ARM® Cortex®-M0 family of 32-bit RISC processors for embedded devices. With its reduced pin count and low power consumption, it is ideal for MCU implementation and boasts exceptional computational performance and sophisticated interrupt response. When it comes to code efficiency, the ARM® Cortex®-M0 processors shine, providing the high performance expected from an ARM core in devices with the 8- and 16-bit memory sizes those processors are typically associated with. The STM32F091xB/xC devices feature an ARM core and are, therefore, compatible with all ARM development environments.

● Cyclic redundancy check calculation unit (CRC)

Codes for cyclic redundancy checks (CRCs) can be generated with a generator polynomial whose value and size are both adjustable. CRC-based techniques are helpful for many purposes, including data integrity verification during transmission or storage. They confirm the honesty of Flash memory within the constraints of the EN/IEC 60335-1 standard. The CRC calculation unit aids in generating a software signature at runtime, which can then be compared to a reference signature generated at link time and stored in a specific memory location.

● Clocks and startup

On reset, the internal RC 8 MHz oscillator is chosen as the default CPU clock, though the system clock is chosen at startup. Its health is tracked if an external 4-32 MHz clock is selected. If a problem is detected, the system will switch off without human intervention.

● General-purpose inputs/outputs (GPIOs)

Each of the general-purpose input/output (GPIO) pins can be set up as an output (push-pull or open-drain), an input (with or without pull-up/pull-down), or an alternate peripheral function. Many general-purpose I/O (GPIO) pins serve dual digital or analog purposes. To prevent accidental changes to the I/O registers, the configuration of the I/Os can be locked if necessary.

● Direct memory access controller (DMA)

DMA1 and DMA2 handle transfers between memory and peripherals and memory and each other with 12 channels each. With circular buffer management provided by the DMAs, the controller no longer needs to rely on user-written code to react when it exhausts its storage. Each channel has its own set of hardware DMA requests, and each channel also has software trigger support. The software handles the configuration, and there is no correlation between the source and destination transfer sizes. All TIMx timers (except for TIM14), the DAC, and the ADC can be used in conjunction with DMA.

● Extended interrupt/event controller (EXTI)

The 32 edge detector lines that make up the eI/E controller’s extended architecture trigger interrupt/event requests and get the machine to start working again. Each line can have its trigger event (rising edge, falling edge, or both) and mask settings. Requests for interruptions are tracked in a “pending” register. For the EXTI to pick up an external line, the pulse width of the line must be smaller than the EXTI’s internal clock period. The 16 outer interrupt lines can connect up to 88 GPIOs.

● Analog-to-digital converter (ADC)

Single-shot and scan conversions are possible with the 12-bit ADC’s 16 external and 3 internal channels (voltage reference, temperature sensor, VBAT voltage measurement). A set of analog inputs will automatically be converted during the scanning process. DMA controllers can also support the analog-to-digital converter. The converted voltage of a single channel, multiple channels, or all channels can be closely monitored with the help of an analog watchdog feature. When the resultant voltage from the conversion falls outside the predetermined limits, an interrupt is triggered.

● Temperature sensor

The voltage VSENSE produced by the temperature sensor (TS) is proportional to the environmental temperature. The temperature sensor is hardwired to the ADC IN16 input channel, which digitizes the sensor’s analog output voltage. Despite the sensor’s impressive linearity, its temperature readings will only be genuinely accurate after they have been calibrated.

The internal temperature sensor that is not calibrated is only useful in applications where it is necessary to detect temperature changes because the offset of the temperature sensor varies from chip to chip due to process variation. All ST temperature sensors are factory calibrated to ensure the most precise readings. ST keeps the factory calibration data for the temperature sensors in a read-only section of system memory.

● High-definition multimedia interface (HDMI) – consumer electronics control (CEC)

To support the Consumer Electronics Control (CEC) protocol, the device incorporates an HDMI-CEC controller (Supplement 1 to the HDMI standard). This protocol allows centralized management of all AV equipment in a given space. The system is designed to function slowly, using as little CPU and RAM as possible. Its clock domain is separate from the CPU clock, allowing the HDMI CEC controller to bring the MCU out of sleep mode when data is received.

● Controller area network (CAN)

With a maximum data transfer rate of 1 Mbit/s, the CAN satisfy the requirements of versions 2.0A and B (active) of the specification. It supports the common 11-bit identifiers used in standard frames and the extended 29-bit identifiers used in extended frames. It has 14 variable-order filter banks, and three transmit mailboxes. Each of the two receive FIFOs has three stages.

● Clock recovery system (CRS)

The internal 48 MHz oscillators of the STM32F091xB/xC can be trimmed automatically by a dedicated block, ensuring that it maintains its optimal accuracy across the entire device’s operational range. The LSE oscillator, an external signal on the CRS SYNC pin, or user-generated software can all contribute to this automatic trimming’s foundational external synchronization signal. Combining automatic trim with manual trimming action can speed up lock-in at startup.

Conclusion

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