24AA64T-I/OT EEPROM

Technical Specifications of 24AA64T-I/OT

Datasheet	24AA64T-I/OT datasheet
Category	Integrated Circuits (ICs)
Family	Memory
Manufacturer	Microchip Technology
Series	–
Packaging	Tape & Reel (TR)
Part Status	Active
Format – Memory	EEPROMs – Serial
Memory Type	EEPROM
Memory Size	64K (8K x 8)
Speed	100kHz, 400kHz
Interface	I2C, 2-Wire Serial
Voltage – Supply	1.7 V ~ 5.5 V
Operating Temperature	-40°C ~ 85°C (TA)
Package / Case	SC-74A, SOT-753
Supplier Device Package	SOT-23-5

24AA64T-I/OT Description

The 24XX64(1) from Microchip Technology, Inc. is an erasable PROM with 64 kilobytes of storage (EEPROM). A two-wire serial interface connects to the device’s single 8K x 8-bit memory block. Its low-voltage design allows it to function at 1.7V, with 1 A standby and 3 mA active currents. The maximum page size that may be written to by the 24XX64 is 32 bytes. Because of functional address lines, a bus can support up to eight devices, each with its own address space of up to 512 Kb.

24AA64T-I/OT Features

• All 24AA64 and 24FC64 devices may operate at 1.7V from a single supply, while 24LC64 devices require 2.5V.
• Interface to the Inter-Integrated Circuit (I2C) that uses a two-wire serial connection.
• Cascading up to eight devices from packages with three address pins is possible.
• The use of Schmitt-Trigger Inputs for Noise Cancellation.
• Eliminating Ground Bounce via Slope Control Output.
• Compatible with both 100 kHz and 400 kHz Clocks.
• FC models have a 1 MHz clock rate.
• Minimum Page Write Time of 5 milliseconds.
• Periodic Erasing and Writing That Is Automatically Controlled.
• A page writes a buffer of 32 bytes.
• Protection against data loss during hardware writes.
• There is no risk of an electrostatic discharge because the voltage threshold is higher than 4000V.
• One million or more read/write cycles.
• Information is kept for longer than two centuries.
• We offer factory-direct programming.
• RoHS Compliant.

Functional Description

A two-wire bus and data transfer protocol are supported by the 24XX64. Devices that broadcast the information onto the bus are called transmitters, while those that receive information are called receivers. The 24XX64 operates as a client on the bus and requires a host device to provide the Serial Clock (SCL), regulate access to the bus, and trigger Start and Stop conditions. The host device controls whether the mode is active; therefore, either the host or the client might be the transmitter or the receiver.

Bus Characteristics

The following bus protocol has been defined:

• Only at times when the bus is not otherwise in use may data transfer begin.
• Data transfer requires a steady line, especially when the clock is high. Any activity on the data line when the clock line is high will be interpreted as a Start or Stop.

Device Addressing

The Chip Select bits are the following three bits of the control byte (A2, A1, A0). Chip Select bits are used to choose which of up to eight 24XX64 devices on the same bus should be accessed. For the device to respond, the logic levels on the A2, A1, and A0 pins must match the Chip Select bits in the control byte. These three digits are the address’s most crucial information.

The client address consists of the last three bits of the 4-bit control code. Address pins are unavailable in SOT-23 and Chip Scale packages. When addressing a device, the Chip Select bits in positions A2, A1, and A0 should all be zero. The Read/Write (R/W) bit, located at the end of the control byte, specifies whether or not the operation is to be read or written. A read operation is chosen when the value is 1. When a value of ‘0’ is input, a write operation will be performed. The first data byte has an address determined by the following two bytes received.

Due to the limited range of valid addresses (A12::A0), the first three address bits are ignored. The Higher Order Bits of the Address are transferred first, followed by the Less Significant Bits. The 24XX64 awaits the Start condition and checks the SDA bus for the sent device type identifier. Once it receives a valid client address and the R/W bit, the client device will send an Acknowledge signal on the SDA channel. The 24XX64 will decide whether to perform a read or write based on the value of the R/W bit.

Contiguous Addressing Across Multiple Devices

With the help of the Chip Select bits A2, A1, and A0, you can connect up to eight additional 24XX64 devices to the same bus and increase the contiguous address space by 512 Kbits. When this occurs, the software can interpret the address bits A0, A1, and A2 of the control byte as A13, A14, and A15, respectively. Reads in sequence cannot traverse device boundaries. If you need to address several devices on the same bus, you can’t use the SOT-23 or Chip Scale package.

Write Operations

● Byte Write

Once the host issues the Start condition, the host transmitter will clock the bus with the control code (four bits), the Chip Select (three bits), and the R/W bit (a logic low). Following the ninth clock cycle, the addressed client receiver will output an Acknowledge bit, signaling the arrival of the high address byte. The high-order byte of the word address is the next byte sent by the host and will be stored in the 24XX64’s Address Pointer.

The Least Significant Address byte comes next. When the 24XX64 sends another Acknowledge signal, the host device can send the data word to be stored at the specified location. After receiving another acknowledgment from the 24XX64, the host issues a Stop condition. It kicks off the 24XX64’s internal write cycle, during which it won’t send out any Acknowledge signals. If the WP pin is high and an attempt is made to write to the array, the device will recognize the command but will not perform a write cycle, write any data, or accept a new order. The internal Address Pointer will advance to the address immediately succeeding the one to which a byte Write instruction was issued.

● Page Write

Like a byte write, the 24XX64 receives a write control byte, word address, and the first data byte. On the other hand, if the host doesn’t generate a Stop condition, it can send up to 31 extra bytes that will be temporarily kept in the on-chip page buffer and then written into memory when the host does generate a Stop condition. The five least significant bits of the Address Pointer, which together make up the byte counter, are automatically increased by one after each incoming word. Word addresses never change in their upper 8 bits.

If the host sends more than 32 bytes before signaling a Stop, the Address Pointer will roll over, and the previous data will be overwritten. When the Stop condition is obtained, an internal write cycle is initiated, just as during a byte write operation. If the WP pin is high and an attempt is made to write to the array, the device will recognize the command but will not perform a write cycle, write any data, or accept a new order.

Conclusion

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