Part Number: DSPIC33EP128MC506-E/PT

Manufacturer: Microchip Technology

Description: Digital Signal Processors & Controllers – DSP, DSC 16B 128KB FL 16KBR 60MHz 64P OpAmps

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Technical Specifications of DSPIC33EP128MC506-E/PT

Datasheet  DSPIC33EP128MC506-E/PT datasheet
Category Integrated Circuits (ICs)
Family Embedded – Microcontrollers
Manufacturer Microchip Technology
Series dsPIC? 33EP
Packaging Tray
Part Status Active
Core Processor dsPIC
Core Size 16-Bit
Speed 60 MIPs
Connectivity CAN, I2C, IrDA, LIN, QEI, SPI, UART/USART
Peripherals Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number of I/O 53
Program Memory Size 128KB (43K x 24)
Program Memory Type FLASH
RAM Size 8K x 16
Voltage – Supply (Vcc/Vdd) 3 V ~ 3.6 V
Data Converters A/D 16x10b/12b
Oscillator Type Internal
Operating Temperature -40°C ~ 125°C (TA)
Package / Case 64-TQFP
Supplier Device Package 64-TQFP (10×10)

A DSC with integrated DSP and improved on-chip peripherals, the 70 MIPS dsPIC® DSC core is the heart of Microchip’s dsPIC33E family of digital signal controllers (DSCs). These DSCs make it possible to create high-performance, precise motor control systems that are more durable, have a more comprehensive operating range, and use less energy. They can manage stepper, brushless DC, AC induction, and permanent magnet synchronous motors. High-performance general-purpose applications are also an excellent fit for these devices.

Product Overview

  • Advanced analogue, high-speed PWM, and op-amps with a 16-bit digital signal controller
  • Architecture that is code-efficient
  • FSCM, WDT, quick wake-up and start-up, and a 1.0% internal oscillator are used for clock control.
  • Power management: Integrated power-on reset, brown-out reset, and low power mode (Sleep, Idle, Doze)
  • PWM at high speed
  • Additional analog features: Flexible and Independent ADC Trigger Sources, an ADC Module, and a CTMU
  • Timers, output comparison, and input recording
  • CRC and PPS communication interfaces, which enable function remapping, are examples of communication interfaces.
  • Memory Access Direct (DMA)
  • Support for developing debuggers: run-time monitoring, tracing, and in-circuit and in-application programming

Product Features

Operating Conditions

  • -40°F to +85°F, DC to 70 MIPS, 3.0V to 3.6V
  • -40°C to +150°C, DC to 60 MIPS, 3.0 to 3.6 V


  • Harvard architecture modified.
  • Optimized Instruction Set for the C compiler.
  • Wide Data Path in 16 bits.
  • Instructions with a 24-bit width.
  • 16×16 Operations for Multiplying Integers.
  • Divide operations using integers of 32/16 and 16/16.
  • There are two 40-bit accumulators with options for rounding and saturation.
  • Multiply and accumulate in a single cycle.
  • Shifts with a single cycle for data up to 40 bits.
  • Fractional Multiplication/Divide Operations 16×16.

High-Speed PWM

  • Three PWM pairs with particular timing are possible.
  • The dead time for edges that are rising and dropping.
  • PWM resolution is 7.14 ns.
  • PWM supports lighting (BLDC, PMSM, ACIM, SRM), PFC, and inverters.
  • Programmable inputs for faults.
  • ADC conversion triggers flexible designs.

Advanced Analog Features

  • ADC module: Selectable between 12-bit, 500 ksps with one S&H and 10-bit, 1.1 Msps with four S&H.
  • Three or more Op-amp/Comparators.
  • Direct connection through Op Amp to the ADC module.
  • Added specialized comparator
  • 32 voltage points on programmable references for comparators.
  • Time Measurement Unit for Charges (CTMU).

Timers/Output Compare/Input Capture

  • 12 timers with multiple uses.
  • Up to two 32-bit timers and five 16-bit timers.
  • Four OC modules can be set up as timers or counters.
  • PTG module with two programmable counters and timers.
  • Timer/counter adjustable 32-bit Quadrature Encoder Interface (QEI) module.
  • Four modules of IC.
  • PTG, a peripheral trigger generator, is used to schedule intricate sequences.

Communication Interfaces

  • UART modules in two (15 Mbps).
  • Four-wire SPI modules in two (15 Mbps).
  • Module CANTM (1 Mbaud) 2.0B assistance.
  • Two SMBus-compatible I2CTM modules with a maximum 1 Mbaud speed.
  • PPS for function remapping.
  • Cyclic Redundancy Check with Programmability (CRC).

Frequently Asked Questions

What is a Digital Signal Controller?

Microcontrollers and digital signal processors are combined to form a digital signal controller (DSC) (DSPs). Like microcontrollers, DSCs feature quick interrupt responses and peripherals focused on control, such as PWMs and watchdog timers, and are typically programmed in the C programming language. However, they can also be programmed in the device’s native assembly language. They integrate DSP features like barrel shifters,  single-cycle multiply-accumulate (MAC) units, and big accumulators, which are familiar to most DSPs. All suppliers have not embraced the term DSC. The phrase was first used in 2002 by Microchip Technology to describe the 6000 series of DSCs, and the majority, but not all, DSC vendors have since adopted it. Infineon and Renesas, for instance, refer to their DSCs as microcontrollers.)

DSCs have many uses, including sensor processing, power conversion, and motor control. Due to their ability to lower the amount of energy used by electric motors and power sources, DSCs are currently advertised as green technology.

According to market research firm Forward Concepts, the top three DSC providers are Texas Freescale, Instruments, and Microchip Technology, in that order of market share (2007). These three companies control most of the DSC industry, with minor shares going to vendors like Infineon and Renesas.

What is a Digital Signal Processor?

The term “digital signal processing” (DSP) describes several methods for enhancing the precision and dependability of digital communications. The theory underlying DSP is rather intricate. DSP essentially clarifies or standardizes the states or levels of a digital signal. The ADSP circuit can distinguish between noise, intrinsically chaotic, and human-made ordered signals.

Circuits used for communication are not noise-free. This holds regardless of the type of information being transmitted or whether the signals are analog or digital. Communication engineers are continually looking for new ways to increase the signal-to-noise ratio in communications systems since noise is their perpetual enemy.

Boosting the sent signal power and increasing receiver sensitivity are two conventional approaches to S/N ratio optimization. Specialized antenna systems can be useful in wireless networks. The sensitivity of a receiving device is significantly increased by digital signal processing. When unwanted signals and noise compete, the effect is most apparent. A practical DSP circuit can occasionally appear to be an electronic miracle worker. But its capabilities are restricted. A DSP circuit cannot identify any order in the chaos, and no signal will be received if the noise is so loud that all signal traces are lost.

An analog-to-digital converter first converts an incoming analog signal to digital forms, such as from a conventional television broadcast station (ADC). The final digital signal consists of two or more levels. These voltages or currents should ideally be constant, precise predictors. The levels aren’t always at the expected levels because the receiving signal contains noise.

The DSP circuit modifies the levels to the appropriate values. This virtually silences the sounds. Using a digital-to-analog converter, the digital signal is then transformed back to analog (DAC).

The ADC and DAC are not required if the received signal is digital, such as computer data. By immediately interacting with the incoming signal and removing noise-induced abnormalities, the DSP reduces the number of errors per unit of time.


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