ENC424J600-I/PT IC

Technical Specifications of ENC424J600-I/PT

Datasheet	ENC424J600-I/PT datasheet
Category	Integrated Circuits (ICs)
Family	Interface – Controllers
Manufacturer	Microchip Technology
Series	–
Packaging	Tray
Part Status	Active
Protocol	Ethernet
Function	Controller
Interface	SPI, Parallel
Standards	10/100 Base-T PHY
Voltage – Supply	3 V ~ 3.6 V
Current – Supply	96mA
Operating Temperature	-40°C ~ 85°C
Package / Case	44-TQFP
Supplier Device Package	44-TQFP (10×10)

ENC424J600-I/PT Description

Using either a flexible parallel interface or the conventional Serial Peripheral Interface (SPI), the ENC424J600 and ENC624J600 are standalone Fast Ethernet controllers. Any SPI or normal parallel port microcontrollers can use them as an Ethernet network interface. Devices of the ENC424J600/624J600 family comply with all mandatory and optional clauses of the IEEE 802.3 standard for 10Base-T and 100Base-TX Ethernet, respectively. Several methods of filtering incoming packets are incorporated into these systems. They support hardware IP checksum computations with an integrated, 16-bit wide DMA for quick data transfer. A set of security engines is made available for use by programs that need to use cryptographic security mechanisms like SSL, TLS, and so on.

With the engines’ ability to compute RSA, Diffie-Hellman, AES, MD5, and SHA-1 algorithms, code size, connection speed, and throughput can all be decreased, while the time and effort required to create firmware can be shortened. The SPI or parallel interface is used for communicating with the microcontroller at data rates between 14 Mbit/s (SPI) to 160 Mbit/s (demultiplexed, 16-bit parallel interface). LEDs show activity and link status, and there are separate pins for transmit, receive, and DMA interruptions. The chip has a substantial 24-KiByte RAM buffer for transmitting and receiving. The host microcontroller could use it for data storage in general.

Communication protocols like TCP can use this memory to store information that may need to be retransmitted later. Each member of the ENC624J600 family has a permanent media access control (MAC) address that has been set into it in advance to facilitate the manufacturing process. This usually frees the final device from undergoing a serialized programming process. The ENC424J600 (44-pin) and ENC624J600 (64-pin) devices are identical in every other respect except for the variety of parallel interfaces they can accommodate.

ENC424J600-I/PT Features

• Correction and detection of polarity.
• Auto-Negotiation is supported.
• Including support for Pause Control Frames.
• Flow Control for Automated Transmit and Receive.
• supports operating in both half- and full-duplex.
• On Collision Programmable Automatic Retransmit.
• Padding that is programmable and CRC generation.
• Automated Error and Runt Packet Rejection with Programmable Rejection.
• Unique MAC Address preprogrammed in the factory.

Detailed Description

● EXTERNAL CONNECTIONS

The ENC424J600/624J600 oscillator devices require a constant 25 MHz clock input for operation. To create this frequency, On the OSC1 and OSC2 pins, attach an external CMOS clock oscillator, or use a parallel resonant, fundamental mode 25 MHz crystal. When used in parallel, a crystal designed for series resonant operation will produce an erroneous frequency. Avoid utilizing resonators or clock generators with a total inaccuracy of greater than 50 ppm to meet the IEEE 802.3 Ethernet timing criteria.

● CLKOUT Pin

The CLKOUT Clock Out pin is available as the host controller clock or as a source for other components. It’s up to you if you want to use it. To generate a 100 MHz internal base clock, a PLL multiplies the 25 MHz clock provided to OSC1. A broad variety of CLKOUT frequencies can be achieved by passing this 100 MHz clock via a customisable postscaler. Due to the PLL multiplier, clock jitter is introduced within the limits of the PLL jitter standard in Section 17.0, “Electrical Properties.” The clock’s duty cycle will be practically optimal thanks to the postscaler.

The COCON bits activate CLKOUT and choose the postscaler (ECON2). As a result, the CLKOUT output and COCON bits are unaffected by resets and power-down modes, resulting in an uncontaminated clock signal. POR allows the CLKOUT feature to run and generate a 4 MHz clock out of the box. The gadget can synchronize its clock with the host computer’s using this setup. The CLKOUT output smoothly changes frequencies whenever a new configuration is written to the COCON bits. No high or low pulses are produced with a period less than the original or new clock.

● Ethernet Signal Pins and External Magnetics

To construct a full IEEE 802.3 compliant 10/100 Ethernet interface, a typical ENC424J600/624J600 device application will call for an Ethernet transformer module, along with a few resistors and capacitors. Two wires make up the Ethernet send interface: TPOUT+ and TPOUT-. These terminals function as a current-mode transmitter and differential pair. Many applications require a 1:1 center-tapped pulse transformer certified for 10/100 or 10/1000 Ethernet operation to produce an Ethernet waveform. Current is constantly sunk via both TPOUT pins when the Ethernet module is enabled and attached to a partner.

Adjusting the ratio of current sunk by TPOUT+ to that by TPOUT-generates a differential voltage on the Ethernet connection when the PHY is transmitting data. Also, TPIN+ and TPIN- make up the differential pair that makes up the Ethernet’s receive interface. These pins are often insulated from the Ethernet connection using a 1:1 center-tapped transformer to ensure IEEE 802.3 compliance and reduce the risk of electrostatic discharge (available in the same package as the TX transformer). To decode incoming signals, the PHY takes a sample of the waveform with an analog-to-digital converter (ADC) that operates at fast speed. Baseline drift correction (useful for 100Base-TX) and automated RX polarity correction are just two of the robustness features implemented by the PHY (applicable to 10Base-T).

All four TX and RX transmission lines must be terminated with 49.9, 1% resistors. The termination resistors should be near the silicon rather than the transformers if the board layout requires long traces between the ENCX24J600 and the Ethernet transformers. Two 6.8 nF 10% capacitors are utilized on the receive signal route. These capacitors and the 49.9 termination resistors constitute an RC high-pass filter that dampens baseline drift. These capacitors are essential for optimal operation and should not be removed or replaced. All the other capacitors block DC current and maintain a steady common-mode voltage across both differential pairs. The inbuilt ADC can handle the weak common-mode signal that is output via the TPIN+/- pins.

Do not attempt to change the TPIN+/- common-mode voltage from the outside, as this is critical for optimal operation. The center tap of the TX transformer can be reached from the power source via the 10 1% resistor. The TPOUT+/- pins are only capable of sinking current; they do not provide a direct voltage as was indicated earlier due to the Current mode drive architecture being used. The transmission waveform is created by the current flowing through the transformer in this way. The power rating of the 10 resistors must be 1/12W or higher since it lowers the amount of heat the PHY must dissipate.

Conclusion

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