Part Number: TCA6424ARGJR

Manufacturer: Texas Instruments

Description: IC XPNDR 400KHZ I2C SMBUS 32UQFN

Shipped from: Shenzhen/HK Warehouse

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Technical Specifications of TCA6424ARGJR

Datasheet  TCA6424ARGJR datasheet
Category Integrated Circuits (ICs)
Family Interface – I/O Expanders
Manufacturer Texas Instruments
Packaging Cut Tape (CT)
Part Status Active
Number of I/O 24
Interface I2C, SMBus
Interrupt Output Yes
Features POR
Output Type Push-Pull
Current – Output Source/Sink 10mA, 25mA
Frequency – Clock 400kHz
Voltage – Supply 1.65 V ~ 5.5 V
Operating Temperature -40°C ~ 85°C
Mounting Type Surface Mount
Package / Case 32-UFQFN Exposed Pad
Supplier Device Package 32-UQFN Exposed Pad (5×5)

TCA6424ARGJR Description

The TCA6424A is a 24-bit I/O expander that uses the I2C interface, which consists of the serial clock (SCL) and serial data (SDA) lines, to enable universal remote I/O expansion across the majority of microcontroller families. Its capacity to operate across a wide variety of power supply voltages (VCC), which vary from 1.65 V to 5.5 V for VPP and SDA/SCL, respectively, is its most impressive characteristic. This qualifies the TCA6424A for SDA and SCL interfaces with contemporary microprocessors and microcontrollers that conserve power. Even if the power supplies for microprocessors and microcontrollers are getting smaller, some printed circuit board components, such as LEDs, still need a 5-V power source.

TCA6424ARGJR Features

  • Input for a reset to active-low ( RESET).
  • output with a low interrupt power and an open drain ( INT).
  • 400 kHz I2C Bus is quick.
  • register for setting up input and output.
  • Enrol in the polarity inversion.
  • internal reset after turning it on.
  • All channels are configured to be inputs during setup.
  • Power-up was bug-free.
  • A noise filter for the SCL and SDA inputs.
  • The largest current drive capacity latching outputs for direct LED driving.
  • Latch-up performance is greater than 100 mA in accordance with JESD 78 class II.

Detailed Description

The TCA6424A has VCCI and can translate voltage levels in both directions. To display the I2C bus VCC level, the VCC of the external SDA/SCL lines must be linked to VCCI. VCCP controls the TCA6424A’s P-port voltage level. The device has three 8-bit registers: input/output/configuration registers and a polarity switch active-high register. The I/Os are initially configured as inputs upon power-up. Still, the system controller can change this by writing to the I/O configuration bits to make them become outputs or inputs.

The appropriate input/output register stores each input/output data, and the Polarity Inversion register can change the polarity of the Input Port register. The system controller has access to every register. The TCA6424A can be reset if it encounters a timeout or other problems by setting a low on the RESET input. While the RESET pin can conduct the same reset/initialization even if the device is not switched off, the power-on reset initializes the I2C/SMBus state machine. It returns the registers to their default state.

The TCA6424A’s open-drain interrupt (INT) output is enabled if an input state deviates from the relevant Input Port register, alerting the system controller that an input state has changed. To recognize the change, the interrupt input of the microcontroller can be connected to the INT pin. Without utilizing the I2C bus, the TCA6424A can act as a straightforward target device that notifies the microcontroller of incoming data on its ports by sending an interrupt signal via the INT pin. Also, the P-port outputs can drive low-current LEDs directly with enough current. Two devices can share one SMBus or I2C bus. The fixed I2C address can be programmed and modified using a single hardware pin (ADDR).

Feature Description

● I/O Port

FETs Q1 and Q2 are disabled when an I/O is set up as an input, creating a high-impedance input. Just 5.5 V over VCC can be added to the input voltage. Depending on how the output port register is configured, Q1 or Q2 is engaged if the I/O is configured as an output. Low-impedance pathways are used to link the I/O pin to either VCC or GND. It is advised not to supply the I/O pin with an external voltage higher than the required voltage levels to guarantee appropriate operation.

● 2 I 2C Interface

The I2C bus is bidirectional and consists of serial clock (SCL) and data (SDA) lines. Each line going to the device’s output stages must have a pullup resistor installed between it and the ground. To initiate data transfer, the bus must first be empty. The start condition transitions from high to low on SDA input/output while SCL input is high, which is sent by a controller to initiate I 2C communication with this device.

The Start condition triggers transmitting the most significant bit (MSB) of the device address byte, followed by the data direction bit (R/W). The SDA input/output goes low during the high of the clock pulse associated with the ACK when the device receives a valid address byte. There must be no changes to the ADDR input of the device being controlled between the Start and Stop states. Only one bit of information is transmitted on the I2C bus at the time of each clock pulse.

The data on the SDA line must remain stable throughout the high pulse of the clock period, as any fluctuations at this time are interpreted as control orders (Start or Stop). The controller has signalled a stop. The SDA input and output go from low to high, while the SCL input is in the high state.

Any number of bytes can be transferred from the transmitter to the receiver between the Start and Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. To keep the SDA line low during the high pulse of the ACK-related clock period, the acknowledging device must pull it down during the ACK clock pulse.

Receivers at a specified address must acknowledge receipt of data bytes. The controller must also respond with an acknowledgement (ACK) whenever it receives data from the target transmitter. The machine won’t function properly if the setup and hold timeframes aren’t followed. The controller’s receiver indicates to the target’s transmitter that the data transfer is complete once the last byte has been sent out (NACK). The controller-receiver will achieve this by putting a high voltage on the SDA line. In this scenario, the controller must make a Stop condition, which requires the transmitter to release the data line.


In conclusion, the TCA6424A offers a versatile solution for expanding remote I/O capabilities with its wide VCC range, 400-kHz Fast I2C Bus, and latched outputs with high-current drive capabilities. Its interrupt output can also simplify communication with microcontrollers. Additionally, ICRFQ, a reputable Chinese electronic wholesaler, offers the TCA6424ARGJR at a fair price with a skilled team and quick delivery to support your project needs. We encourage you to check out ICRFQ to discover how they can help with your next project.

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