TPA3112D1PWPR Audio Amplifiers

Technical Specifications of TPA3112D1PWPR

Datasheet	TPA3112D1PWPR datasheet
Category	Integrated Circuits (ICs)
Family	Linear – Amplifiers – Audio
Manufacturer	Texas Instruments
Series	SpeakerGuard?
Packaging	Tape & Reel (TR)
Part Status	Active
Type	Class D
Output Type	1-Channel (Mono)
Max Output Power x Channels @ Load	25W x 1 @ 8 Ohm
Voltage – Supply	8 V ~ 26 V
Features	Differential Inputs, Short-Circuit and Thermal Protection, Shutdown
Mounting Type	Surface Mount
Operating Temperature	-40°C ~ 85°C (TA)
Supplier Device Package	28-HTSSOP
Package / Case	28-TSSOP (0.173″, 4.40mm Width) Exposed Pad

Description of the TPA3112D1PWPR

A bridge-tied speaker can be driven by the TPA3112D1PWPR, a 25-W effective Class-D audio power amplifier.  Advanced EMI Suppression Technology enables EMC standards while using low-cost ferrite bead filters at the outputs. The SpeakerGuard speaker protection system has a DC detection circuit and an adjustable power limiter. To set a voltage rail lower than the chip supply and reduce the current flowing through the speaker, utilize the adjustable power limiter. When input capacitors are destroyed, or there are input shorts, the DC detect circuit checks the frequency and amplitude of the PWM signal and turns off the output stage.

A mono speaker can be driven at a low 4 with the TPA3112D1PWPR. When playing music, the TPA3112D1’s excellent efficiency (> 90%) negates the need for an external heat sink. The outputs are completely shielded against shorts to GND, VCC, and other outputs. An auto recovery feature is part of the heat protection and short-circuits protection.’

Features for the TPA3112D1PWPR

• From a 24-V supply, 25-W into an 8- load at less than 0.1% THD+N.
• 20-W at 10% THD+N into a 4- load from a 12-V supply
• Heat Sinks are unnecessary because of 94% efficient Class-D operation under 8-load.
• Wide Supply Voltage Range Enables 8 to 26 V Operation.
• Operation Without Filters
• Adjustable power limiters and DC protection are also included in SpeakerGuardTM speaker protection.
• Easy Board Layout is Made Possible by Flow-Through Pin Out.
• Thermal solid protection with an auto-recovery option and pin-to-pin short circuit protection.
• Outstanding THD+N/Pop-Free Performance.
• There are four pickable fixed gain settings.
• Differential Inputs.

Detailed Description

The TPA3112D1PWPR can operate with just one power supply ranging from 8 V to 26 V, simplifying system design. The gate driver, digital, and low-voltage analog circuitry operate at appropriate voltage levels thanks to an internal voltage regulator. Additionally, built-in bootstrap circuitry is used to accommodate all circuitry that needs a floating voltage supply, i.e., the high-side gate drive, with integrated bootstrap diodes that only need an external capacitor for each half-bridge.

The TPA3112D1PWPR  can operate with just one power supply ranging from 8 V to 26 V, simplifying system design. The gate driver, digital, and low-voltage analog circuitry operate at appropriate voltage levels thanks to an internal voltage regulator. Additionally, built-in bootstrap circuitry is used to accommodate all circuitry that needs a floating voltage supply, i.e., the high-side gate drive, with integrated bootstrap diodes that only need an external capacitor for each half-bridge.

Each bootstrap pin (BSx) must be linked to the power-stage output pin with a tiny ceramic capacitor for the bootstrap circuit to function correctly (OUTx). An internal diode between the bootstrap pins and the gate-drive power supply pin (GVDD) charges the bootstrap capacitor when the power-stage output is low. The bootstrap capacitor potential is pushed above the output potential when the power-stage output is high, providing an appropriate voltage supply for the high-side gate driver. For the bootstrap supply, TI suggests ceramic capacitors with a minimum 220-nF capacitance, size 0603 or 0805, in an application with PWM switching rates of about 310 kHz.

These capacitors ensure enough energy storage, even during low frequency audio signals clipped, so that the high-side power stage FET (LDMOS) can remain entirely on for the rest of its ON cycle. Pay close attention to the component choice, PCB layout, and routing of the power-stage power supply. Each PVCC pin should be decoupled with ceramic capacitors positioned near each supply pin for the best electrical performance, EMI compliance, and system reliability. TI advises adopting the TPA3112D1 EVM’s PCB layout.

Feature Description

Gain Setting Through the Gain0 And Gain1 Inputs Using the input terminals GAIN0 and GAIN1, the TPA3112D1’s gain is controlled. These gain terminals, terminals 1 and 14, and all other terminals must have a 10V/ms maximum voltage slew rate. Use a 100-k resistor in series with the terminals to increase slew rates.

SD Operation

The TPA3112D1 uses a shutdown mode of operation intended to reduce supply current (ICC) to the lowest possible level while not in use to conserve power. When using the amplifier, the SD input terminal typically should be high (the trip point is listed in the specification table). The outputs become muted, and the amplifier switches to a low-current mode when SD is pulled low. Never leave SD unplugged because the functionality of the amplifier would be unpredictable. Place the amplifier in shutdown mode before eliminating the power supply voltage for the optimum power-off pop performance.

PLIMIT

The power can be limited to levels below what the supply rail will allow by adjusting the voltage at pin 10. To adjust the voltage at the PLIMIT pin, add a resistor divider from GVDD to the ground. An external reference may also be employed if a stricter tolerance is necessary. In addition, connect pin 10 to the ground with a 1-F capacitor. The PLIMIT circuit constrains the peak-to-peak voltage of the output. This limit can be compared to a virtual voltage rail lower than the supply connected to PVCC. The voltage on this virtual rail is four times that at the PLIMIT pin. The maximum output power can be calculated using this output voltage for a particular maximum input voltage and speaker impedance.

The PLIMIT circuits constrain the output peak-to-peak voltage. The limitation is accomplished by setting a preset maximum duty cycle. Compared to the supply connected to PVCC, this restriction can be seen as a lower virtual voltage rail. The voltage at the PLIMIT pin is quadrupled by this virtual rail. This output voltage can be used to determine the maximum output power for a particular maximum input voltage and speaker impedance.

GVDD Supply

The PLIMIT voltage divider circuit and the output complete bridge transistors’ gates are powered by the GVDD supply. At this pin, connect a 1-F capacitor to the ground.

DC Detect

The TPA3112D1 contains circuitry that shields the speakers from DC that faulty input capacitors or input board faults could bring on. A DC detect fault will be recorded as a low state on the FAULT pin. The outputs’ state will be changed to Hi-Z by the DC Detect fault, which will also force the amplifier to shut down.

The PVCC supply must be cycled to clear the DC Detect. A DC detect fault CANNOT be cleared by cycling SD. A DC Detect Fault is generated when the output differential duty cycle is greater than 14% (for instance, +57%, -43%) for more than 420 ms at the same polarity. This feature shields the speaker from strong DC and AC currents with frequencies below 2 Hz. Hold the SD pin low during power-up until the input signals are stable to prevent annoying faults brought on by the DC detect circuit. Additionally, be careful to match the impedance at the positive and negative inputs to prevent bothersome DC detect faults.

Conclusion

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