Part Number: XCF08PFS48C

Manufacturer: Xilinx

Description: FPGA – Configuration Memory Flash 8Mb PROM (ST Micro)

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Technical Specifications of XCF08PFS48C

Datasheet  XCF08PFS48C datasheet
Category Integrated Circuits (ICs)
Family Memory – Configuration Proms for FPGAs
Manufacturer Xilinx Inc.
Packaging Tray
Part Status Active
Programmable Type In System Programmable
Memory Size 8Mb
Voltage – Supply 1.65 V ~ 2 V
Operating Temperature -40°C ~ 85°C
Package / Case 48-TFBGA, CSPBGA
Supplier Device Package 48-CSP (8×9)

XCF08PFS48C Description

System-in-package programmable configuration read-only memories (PROMs) are what Xilinx calls their “Platform Flash” series. These PROMs, ranging in density from 1 to 32 MB, are a simple, inexpensive, reprogrammable option for storing substantial Xilinx FPGA configuration bitstreams. The 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM are both Platform Flash PROM series parts. The XCFxxS variant provides Master Serial and Slave Serial FPGA configuration through its 4 Mb, 2 Mb, and 1 Mb PROMs.

XCF08PFS48C Features

  • Configuration of Xilinx® FPGAs Using In-System Programmable PROMs
  • Low-Power, Long-Lasting NOR Flash Memory Utilizing an Advanced CMOS Technology that Can Withstand 20,000 Write/Erase Cycles
  • -40 degrees Celsius to 85 degrees Celsius (-45 degrees Fahrenheit to 185 degrees Fahrenheit) Operating Temperature Range, Per IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) (JTAG) Help for JTAG Command Development, Prototyping, and Testing Start of a Common FPGA Configuration That Can Cascadingly Store Bitstreams That Are Longer or More Numerous
  • Constant Boundary-Checking (JTAG) I/O Logic Supply (VCCJ)
  • Designs for I/O Pins that Work with Voltages from 1.8V to 3.3V Facilitate the Employment of Xilinx ISE® Alliance and FoundationTM


This programmable NOR flash device is known as the Platform Flash PROM. To re-program the device, it is necessary to perform an erase operation before a program operation. If you want to ensure that the data from your programmer source made it onto your Platform Flash PROM correctly, you should run a verify operation after the program one. There are multiple possible programming solutions.

● System-Level Coding

The standard 4-pin JTAG protocol can program a single In-System Programmable PROM or multiple PROMs in a daisy-chain configuration.

In-system programming allows for rapid iteration during the design process by removing the need for repackaging or re-socketing devices. Xilinx iMPACT software and a Xilinx download cable, a JTAG-compatible board tester,  a third-party JTAG development system, or a simple microprocessor interface that emulates the JTAG. Instruction sequences can all be used to transfer the programming data sequence to the device. Serial vector format (SVF) files can be generated by the impacted program and imported into other programs that support the format, such as automatic test equipment. CEO output is set to High during in-system programming. In-system programming maintains all different results in a high-impedance state or at clamp levels. During in-system programming, the CLK, CE, CF, OE/RESET, BUSY, EN EXT SEL, and REV SEL[1:0] input pins, along with any others, are disregarded. Within the specified voltage and temperature parameters, in-system programming is fully supported.

A Platform Flash PROM’s initial memory image can be programmed by a third-party device programmer in a conventional manufacturing environment before the PROMs are assembled onto boards. Please contact your preferred third-party programmer vendor if you require Platform Flash PROM assistance. On the Xilinx website page for Third-Party Programmer Device Support, you can find a selection of third-party programmer vendors who support Platform Flash PROM.

● Design Security

Security features in the Xilinx in-system programmable Platform Flash PROM devices prevent even authorized JTAG access to the FPGA’s programming data. To further safeguard against accidental JTAG writing, the XCFxxP PROMs can be programmed to disable this feature.

● Read Protocol

The user can set the read-protect security bit to prevent the internal programming pattern from being read or copied via JTAG. Write access is not blocked by read-only access. When the read protects security bit is set on an XCFxxS PROM, it applies to the entire device and cannot be reset without a full erase. Each design revision of the XCFxxP PROM can have its read-protect security bit, and clearing the bit requires erasing that revision.

● Enhancements to the XCFxxP’s In-Built Oscillator

Internal oscillators are available on the 8/16/32 Mb XCFxxP Platform Flash PROMs and can power the FPGA configuration interface’s CLKOUT and DATA pins. When programming the PROM, you can enable the internal oscillator and change its frequency from the standard rate to a lower one. For advice on selecting an internal oscillator, see UG161, Platform Flash PROM User Guide, specifically the “XCFxxP Decompression and Clock Options” section.


To ensure that the PROM’s source synchronous clock is correctly aligned with the data on the configuration interface, the PROM can be programmed to enable the CLKOUT signal. This is the case for the 8/16/32 Mb XCFxxP Platform Flash PROMs. The CLK input pin or the internal oscillator are the two potential origins of the CLKOUT signal. During the process of programming the PROM, the input clock source is decided. The CLKOUT output signal is available on the rising edge.

● Decompression

All 8/16/32 Mb XCFxxP Platform Flash PROMs have an integrated data decompressor that works with Xilinx’s cutting-edge compression technology. Using the impacted program, compressed Platform Flash PROM files are generated from the desired FPGA bitstream(s). When configuring an FPGA with a compressed bitstream programmed into an XCFxxP PROM, you are limited to using either the Slave Serial or Slave SelectMAP (parallel) configuration modes. Compression rates are conditional on several factors, such as the type of device being compressed and the contents of the targeted design.

Once the PROM has been programmed, the decompression option can be activated. Before sending the clock and data to the FPGA’s configuration interface, the PROM decompresses the data. When Decompression is activated, the configuration interface clock signal must be driven into the configuration clock input pin of the target FPGA via the Platform Flash clock output pin (CLKOUT) (CCLK). CLKOUT can be connected to the PROM’s CLK input pin or the internal oscillator.

Any target FPGA attached to the PROM must run in Slave Serial mode or Slave SelectMap (parallel) mode in the configuration chain. Decompressing data transforms the CLKOUT signal into a frequency-capped, decompressed clock output. Since the CLKOUT pin is set to a high-Z state when the decompressed data is not yet ready, it must be pulled High externally to provide a known state. When Decompression is activated, the BUSY input is immediately turned off.

When CE is not asserted, the PROM goes into a low-power standby mode (High). Regardless of the OE/RESET input sets, the address counter is cleared, the CEO is driven High, and the remaining outputs are made to have a high impedance when in standby mode. If you want your device to stay in low-power standby mode, you need to prevent TCK from going Low and prevent the JTAG pins TMS, TDI, and TDO from going Low (High or Low).


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